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    ID
    Family
    Category
    Related To
  • ECP3 : How long does it take for the SerDes TX PLL to lock?
    81
    LatticeECP3
    Architecture
    SERDES/PCS
  • What do I do with VCCIBx connection of the SERDES channel in TX only mode?
    82
    LatticeECP3
    Architecture
    SERDES/PCS
  • What are the pin location requirements when using an input clock to capture input data?
    202
    All FPGA
    Customer Board Design
    Layout Review
  • All FPGA: What is the initial logic level of a register after power-up?
    204
    All FPGA
    Architecture
    General Logic
  • How to solve the issue of "ispVM System  doesn't detect  parallel port ISP Download Cable" ?
    209
    All FPGA
    Device Programming
    ispVM System
  • Diamond: How do user get a reasonable I/O timing report when PLL phase shift is very large?
    200
    All FPGA
    Implementation
    Timing Analysis
  • What are the required locations for the 7:1 LVDS pins on the LatticeXP2, LatticeECP2/M or…
    203
    All FPGA
    Customer Board Design
    Layout Review
  • IO Simulation: How to simulate open drain IO/s?
    241
    All Devices
    Entry
    Mixed Language
  • MachXO: How is the TSALL pin used in the MachXO?
    246
    MachXO
    Architecture
    IO
  • What is the difference between an ispGAL and a GAL device?
    245
    GAL/ispGAL
    Architecture
    General Logic
  • MachXO: Is an external pull up required on the SleepN pin?
    247
    MachXO
    Architecture
    IO
  • All FPGA: How does the output register and read enable (RDEN) signal affect Dual Clock…
    235
    All Devices
    Architecture
    Memory EBR/Distributed
  • ispLEVER: Why are the registers of the design being clocked at a faster rate than intended?
    231
    All Devices
    Implementation
    Synplicity
  • LatticeECP3: Can LatticeECP3 devices support sub-LVDS IO?
    2330
    LatticeECP3
    Architecture
    IO
  • Diamond:  In Lattice Diamond, what is the difference between a Pin Layout File and a Pin Out file?
    2378
    All FPGA
    Implementation
    Design Planner
  • LatticeECP3:  Can the bitstream used for the regular device be programmed in the low power device of…
    2372
    LatticeECP3
    Device Programming
    Diamond Programmer
  • Platform Manager 2 & L-ASC10: What are the allowed input currents for the Power Manager II VMON and…
    2377
    Power Manager II
    Customer Board Design
    Schematic Review
  • Lattice Mico: In a Mico System Builder(MSB) project, can the characters transmitted through the UART…
    2345
    All Devices
    Implementation
    Mico32(MSB)
  • [MachXO2]: What is the maximum size of the SSPI Embedded SEA/SED data files?
    2340
    All FPGA
    Device Programming
    ispVM System
  • MachXO2: Why does the Lattice software picks VCCIO bank voltages smaller than 3.3V when all my…
    2347
    MachXO2
    Architecture
    IO
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