CSI-2/DSI D-PHY Receiver

Convert MIPI CSI-2/DSI Data Streams to Parallel Data

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Related Applications

The Mobile Industry Processor Interface (MIPI®) D-PHY was developed primarily to support camera and display interconnections in mobile devices, and it has become the industry’s primary high-speed PHY solution for these applications in smartphones. It is typically used in conjunction with MIPI Camera Serial Interface-2 (CSI-2) and MIPI Display Serial Interface (DSI) protocol specifications. MIPI D-PHY meets the demanding requirements of low power, low noise generation, and high noise immunity that mobile phone designs demand.

MIPI D-PHY is a practical PHY for typical camera and display applications. It is designed to replace traditional parallel bus based on LVCMOS or LVDS. Lattice’s submodule may be used for applications requiring a D-PHY receiver in the FPGA logic.

Features

  • Compliant with MIPI DSI v1.1, MIPI CSI-2 v1.1 and MIPI D-PHY v1.1 specifications
  • Supports MIPI DSI and MIPI CSI-2 interfacing up to 6 Gb/s
  • Supports 1, 2 or 4 MIPI D-PHY data lanes
  • Supports non-burst mode with sync events for transmission of DSI packets only
  • Supports LP (low power) mode during vertical and horizontal blanking

Block Diagram

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
CSI-2/DSI D-PHY Receiver Submodule IP
FPGA-IPUG-02025 1.0 7/31/2017 PDF 2 MB


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