Camera applications typically feature an Image Sensor and an Image Signal Processor. In the past, a simple CMOS parallel interface was sufficient to support the resolutions and frame rates for camera applications.
Traditional Sensor – ISP Interface
As sensor resolutions and frame rates have increased, the traditional CMOS parallel interface is no longer capable of handling the increased bandwidth requirements. For this reason vendors are now adopting differential interfaces for higher resolution and faster frame rate sensors. Each sensor vendor has chosen to implement different serial interface I/Os, various data widths, disparate frame configurations and unique clocking structures. Because of these varied interfaces, Image Signal Processors (ISP) will be challenged to implement all of these unique interfaces. Many ISPs are capable of handling the higher resolution and frame rates, but may only do so via a faster parallel interface.
With a low cost Lattice FPGA customers can perform bridging of sensors using high speed serial interfaces to ISPs that still use the parallel interface as shown in the figure below.
Evolving Sensor – ISP Interface
Reference Designs
- MIPI CSI-2 to Parallel Bridge
- Dual HiSPi Sensor Interface Bridge
- Aptina Sensor With HiSPi To Parallel Sensor Bridge
- Panasonic Area Sensor-to-Parallel Bridge
- Sony IMX136/104 Sensor With subLVDS To Parallel Sensor Bridge