 Download the datasheet |
The syn1588® VIP clock synchronization SoC IP Core enables a cost effective yet highly integrated single chip IEEE1588 solution. Only a single external Ethernet PHY is required to create a fully functional IEEE1588 node.
Due to its highly efficient PTP stack implementation, the syn1588® VIP may be used in a variety of different timing applications. It fully supports the default as well as the telecom, and power profile both in layer2 or layer3 communication mode.
The syn1588® VIP generates a highly accurate 1pps signal together with a user-programmable frequency output phase-locked to the synchronized local clock. Additionally, time stamps are generated and stored in a local buffer memory in case an external event occurs at an input pin.
The unit may assume the role of a GPS timing receiver in a system without the need for an external antenna. If connected to a PTP Grand Master, it will switch to slave mode synchronizing its local clock to the master. Apart from a 1 pps signal, it will generate an NMEA compatible data stream on the serial interface effectively acting as a GPS timing receiver.
Equally well, the syn1588® VIP may be attached directly to a GPS timing receiver via its event input and its serial interface. It will synchronize its local clock to the GPS time assuming the role of a grand master to the network it is attached to.
The syn1588® VIP is available as:
The syn1588® VIP - Fully Integrated Clock Solution is supported on both LatticeECP3 and LatticeECP2M FPGA families.
This diagram shows the syn1588® .
Please contact Oregano directly at: http://www.oregano.at/eng
© Lattice Semiconductor Corporation 2012
