The syn1588® VIP Dual SoC IP core offers unparalleled integration density providing the end user with a versatile 2-port PTP node. Each port may operate in any PTP role using either the default, the power, or the telecom profile. The combination of all necessary hard and software modules into one single chip enables a cost effective, highly-integrated, single chip, multi-port IEEE1588 solution. Only a single external Ethernet PHY for every port is required to create a fully functional IEEE1588 node.
Every port of device will generate an accurate high precision 1-pps signal together with a user-programmable frequency output phase locked to the synchronized local clock of the respective port. Additionally, time stamps are generated in case an external event occurs on a dedicated input pin.
As every port may be configured separately according to IEEE1588, the syn1588® VIP Dual supports a variety of possible implementation scenarios:
- Slave-Master: One port is configured as a slave-only node attached to an external grand master thus maintaining the connection to an external network. While the other port will run in master mode supplying the local network with accurate time information. The time information will be transferred internally between the two ports.
- Hot-Stand-by: Both ports, if configured as slaves, may be connected to different external masters. Both ports will generate pps signals together with phased-locked output frequencies and feed their host systems. In case one master fails, the 1 pps feed can be switched over.
- Different-Profiles: One port may be run in slave mode being connected to an external multicast master, while the other port will run in unicast master mode supporting the telecom profile. Alternatively, the second port may be operated in power profile using the peer-delay mechanism transmitting messages at a pre-defined rate.
- Redundant-Master: Both ports may be connected to an external GPS timing receiver via their respective 1 pps input pins and a common shared serial input stream. Such a configuration permits building redundant master structures. Additionally, it is possible to build a split network topology if the ports are connected to distinct LANs.
The syn1588® VIP Dual - Fully Integrated Clock Solution is supported on both LatticeECP3 and LatticeECP2M FPGA families.
Block Diagram
This diagram shows the syn1588® VIP Dual SoC IP core.
Features
- Two independent PTP ports with share local oscillator
- Configurable role per port
- Configurable profile per port
- 10/100/1000 Mbps Ethernet MAC (IEEE802.3 2000)
- IEEE1588-2008 hardware timestamping
- 2 IEEE1588 hardware clocks
- IEEE1588-2008 Layer 2 compliant
- IEEE1588-2008 Layer 3 compliant (UDP, ARP, DHCP)
- Clocks accuracy better than 50 ns
- syn1588® PTP stack binary included (running on integrated 8-bit CPU core)
- Shared program ROM
- 2x 1pps outputs
- 2x Frequency outputs
- 2x Event input
- In layer 3 mode each node may be controlled remotely via IEEE1588 management messages
- Optional analog PLL using VXCOs
Applications
- Test and Measurement
- Industrial Automation and Control
- Telecom
- Military
- Power Industry
Evaluation and Licensing Terms
Please contact Oregano directly at: http://www.oregano.at/eng
© Lattice Semiconductor Corporation 2012
