HDR-60 Video Camera Development Kit

The HDR-60 Video Camera Development Kit is a fully production-ready High Dynamic Range (HDR) camera, designed to fit into commercially available camera housings. The hardware is intended to support full 1080p resolution at 60 frames per second in streaming mode through the FPGA, without the need for an external frame buffer.

The integrated IONOS Image Signal Processing (ISP) IP pipeline from Lattice partner Helion GmbH provides end-to-end ISP support from sensor to displayable image and incorporates sensor interfacing, defective pixel correction and 2D noise reduction, high-quality 5 x 5 DeBayer, Color Correction Matrix, Fast Auto Exposure, Auto White Balance, HDR, Gamma Correction and Overlay (both character and graphics). Lattice HDMI PHY IP enables output to HDMI/DVI monitors.

The HDR-60 Video Camera Development Kit provides the industry’s fastest Auto-Exposure, very high quality Auto White Balance and HDR greater than 120dB. On-board Broadcom Broadreach™ PHY enables support for Ethernet over coax up to a length of 700 meters. The hardware can support up to 16-megapixel sensors, can hold up to two sensors simultaneously and can be easily programmed via a standard low-cost USB cable.

The Kit consists of two boards, the long HDR-60 Base Board and the square Nanovesta Sensor Board mounted on top of the Base Board. The base board is populated with a LatticeECP3-70, while the sensor board is equipped with an Aptina 720p High Dynamic Range (HDR) sensor. The hardware, however, is designed to support full 1080p resolution at 60 frames per second.

The Kit incorporates a plug-n-play demo that runs right out of the box at 60fps when connected to a HDMI or DVI monitor. It is designed to jump-start the design efforts of camera manufacturer's planning to take advantage of the high-performance and low-power digital signal processing capabilities of Lattice FPGAs, the demo bitstream, board schematics and Gerber files that are available and free of charge to all purchasers of the Kit.

While the Kit is populated with a LatticeECP3-70 in order to provide ample space for a camera manufacturer's integration of their own IP, the entire IONOS HDR Image Signal Processing (ISP) pipeline is capable of fitting into a LatticeECP3-35 device. This, coupled with the fact that the ISP pipeline needs no external frame buffer as well as the low power consumption of the LatticeECP3 FPGA, means that HDR-60 based cameras are extremely low cost to build and operate.

Features

  • FPGA-based Image Signal Processing
  • Fully production-ready HDR camera design
  • 1080p capable at 60 frames per second
  • Supports up to 16 megapixel sensors
  • Supports up to two sensors simultaneously
  • Full 60fps in streaming mode, needs no external frame buffer
  • Fast auto exposure instantly adjusts to changing light 
  • Greater than 120 dB High Dynamic Range (HDR) performance
  • Direct HDMI / DVI output from FPGA
  • Extremely low latency
  • Comprehensive image processing IP library
  • On-board Broadcom® BroadreachTM PHY enables IP over coax 
  • On-board FTDI chip provides easy programming via low cost USB cable

Kit Contents

  • HDR-60 Base Board
  • 9MT024 NanoVesta Headboard (included with -DKN version only)
  • Two USB cables
  • HDMI cable
  • HDMI-DVI adapter
  • 12V power supply (international voltage)
  • QuickStart Guide

Board Photos

Top View, HDR-60 Base Board with NanoVesta Head Board

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Top View, HDR-60 Base Board without NanoVesta Head Board

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Side View, HDR-60 Base Board with NanoVesta Head Board

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Ordering Information

  • Ordering Part Number: LFE3-70EA-HDR60-DKN
    Includes HDR-60 Base Board and 9MT024 NanoVesta Head Board
  • Ordering Part Number: LFE3-70EA-HDR60-EVN
    Includes HDR-60 Base Board only, no NanoVesta Head Board included.
  • Click here to find an authorized Lattice distributor near you
  • Click here to order now from the Lattice Online Store

Documentation

Quick Reference Technical Resources Information Resources Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
HDR-60 Base Board - Revision A User's Guide EB59 01.1 8/6/2012 PDF 3.1 MB
HDR-60 Base Board - Revision B User's Guide EB70 1.2 4/9/2014 PDF 3.4 MB
HDR-60 Video Camera Development Kit Quick Start Guide QS010 11/6/2012 PDF 1.3 MB
MachXO2 Dual Sensor Interface Board User's Guide EB69 1.1 1/5/2012 PDF 2.4 MB
MT9M024 NanoVesta Head Board User's Guide EB63 01.1 5/8/2012 PDF 1 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
HiSPi-to-Parallel Sensor Bridge RD1120 1.3 4/1/2014 PDF 734.9 KB
HiSPi-to-Parallel Sensor Bridge - Source Code RD1120 1.3 4/9/2014 ZIP 342.6 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Camera Solutions Product Brief IO232 4/25/2013 PDF 2.8 MB
Dual Image Sensor Product Brief 4/3/2012 PDF 1.2 MB
HDR-60 Video Camera Development Kit Product Brief I0213 4/6/2012 PDF 1.9 MB
HDR-60 Video Camera Development Kit Product Brief (Chinese Language Version) I0213C 4/1/2012 PDF 2.3 MB
IP Suites for LatticeECP3 - News Brief NB101 2/4/2011 PDF 458.8 KB
LatticeECP3 Family Product Brochure I0198 H 5/29/2012 PDF 2.7 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
HDR-60 BOM Rev A 2/22/2011 XLS 57.5 KB
HDR-60 BOM Rev B 1/25/2012 XLS 66.5 KB
HDR-60 Default Programming Bit Streams and Graphical User Interface files 1/28/2013 ZIP 7.6 MB
HDR-60 Gerber Files Rev B 1/25/2012 ZIP 1.1 MB
HDR-60 PCB Layout Rev A 2/22/2011 ZIP 2.1 MB
HDR-60 PCB Photoplots Rev A 2/22/2011 ZIP 1.1 MB
HDR-60 PCB Rev B 1/25/2012 ZIP 2.1 MB
HDR-60 Schematic Rev A 2/22/2011 ZIP 801.9 KB
HDR-60 Schematic Rev B 3/1/2012 ZIP 659.5 KB
MN34041 Sensor NanoVesta Headboard Bitstream 3/21/2012 BIT 2.5 MB
MT9M024 NanoVesta Rev B Layout 5/6/2011 ZIP 897.9 KB
NanoVesta BOM Rev A 2/22/2011 XLS 34 KB
NanoVesta BOM Rev B 1/20/2012 XLS 41 KB
NanoVesta PCB Layout Rev A 2/22/2011 ZIP 1.2 MB
Nanovesta PCB Photoplots Rev A 2/22/2011 ZIP 759.8 KB
NanoVesta Photoplots Rev B 1/20/2012 ZIP 714.3 KB
NanoVesta Schematic Rev A 2/22/2011 ZIP 357.5 KB
NanoVesta Schematic Rev A or B 1/20/2012 ZIP 465.1 KB
Using Lattice HDR-60 With Aptina DevWare 3/15/2011 ZIP 1.1 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Helion ISP Pipeline 5/22/2013 JPG 124.1 KB


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