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ID: 345
Case Type: faq
Category: Lattice IP/Reference Design
Related To: Tri-Speed Ethernet MAC
Family: All FPGA

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What do I need in addition to the Tri-Speed Mac (TSMAC) core on the board (PHY, magnetics etc)?

The Tri-Speed Ethernet Media Access (TSMAC) IP core acts as a bridge between a client interface and an Ethernet Physical Link MII, or GMII interface.  In order to transmit and receive Ethernet data,you must attach the TSMAC to an Ethernet PHY device. 


There are different ways to attach to an Ethernet PHY and different ways to attach the Ethernet PHY to physical media.


Here are some examples :



  1. TSMAC GMII/MII->Ethernet PHY->RJ45: The TSMAC GMII/MII interface connects to an external Ethernet PHY. The PHY converts GMII/MII data to 10/100/1000 BASE-T (copper) data.  Inductive isolation is required between the PHY and the RJ45 connector.  Most RJ45 jacks now have the isolation inductors and spark gap capacitors built-in. 
  2. TSMAC->SGMII/GbE PCS-IP>Multiple Options: This applies to LatticeSC/LatticeECP2M and LatticeECP3 devices. The TSMAC GMII interface connects to the FPGA's internal Physical Coding Sublayer block.  The data presented to the PCS is, in most cases, converted into 8b10b SERDES data.  The 8b10b SERDES data can be used several ways:


    • SMAs: You can send SERDES data directly to SMA connectors.  The SMA connectors allow for a good deal of flexibility for connecting to other devices. You can connect SMA connectors to Ethernet PHY evaluation boards, or direct chassis to chassis connections.  In most cases the data will be 1000Base-X GbE traffic.
    • SFP: You can connect a Small Form Pluggable (SFP) module connector and cage to the SERDES IO of the FPGA. SFP modules typically contain an Ethernet PHY device.  The Ethernet PHY device, instead of being connected to an RJ45 connector is attached to an optical transmitter/receiver, or to a special copper cable.  In most cases the data will be 1000Base-X GbE traffic.
    • Ethernet PHY: You can attach the SERDES data from the FPGA to a SERDES capable Ethernet PHY like the Marvell 88E1111.  In this case, the PHY is flexible enough to act as a bridge between GbE or SGMII SERDES link on one end and a 1000/100/10BASE-T copper link on the other. 
    • SGMII Direct Connect: You can directly connect the SGMII SERDES data from one FPGA to another SERDES FPGA with a TSMAC core. This mode of operation can be used for backplane connections within a chassis. This removes the need to add an Ethernet PHY. 

For the schematic of a evaluation board that includes both an LatticeECP3 FPGA (with TSMAC, SGMII PCS to SERDES) and an on-board Marvell 88E111 PHY, please look at the LatticeECP3 Serial Protocol Evaluation Board.

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