莱迪思解决方案

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  • CrossLinkU-NX评估板

    Board

    CrossLinkU-NX评估板

    CrossLinkU-NX评估板是一个使用CrossLinkU-NX器件进行通用应用开发的平台,CrossLinkU-NX器件是首款具有硬核USB2/3(5Gbps)接口的FPGA。
    CrossLinkU-NX评估板
  • USB 2.0/3.2 IP核

    IP Core

    USB 2.0/3.2 IP核

    莱迪思USB 2.0/3.2 IP核提供了一种连接USB主机的解决方案,适用于莱迪思CrossLink-NX FPGA最新器件。
    USB 2.0/3.2 IP核
  • USB到I/O聚合和桥接参考设计

    Reference Design

    USB到I/O聚合和桥接参考设计

    USB到I/O桥接参考设计为支持USB的FPGA提供即插即用外设扩展,还支持从USB到I2C、SPI和GPIO的信号协议转换。
    USB到I/O聚合和桥接参考设计
  • USB到I/O聚合和桥接演示

    演示

    USB到I/O聚合和桥接演示

    USB到I/O聚合和桥接演示展示了莱迪思FPGA的功能,并加速了USB 2.0/3.2(5Gbps)接口创新。
    USB到I/O聚合和桥接演示
  • Crosslink-NX PCIe桥接板上的PCIe基础演示

    演示

    Crosslink-NX PCIe桥接板上的PCIe基础演示

    该PCIe基础演示可以控制三个7段LED,并通过PCIe插槽操作FPGA的片上存储器。
    Crosslink-NX PCIe桥接板上的PCIe基础演示
  • PCIe Colorbar Demo for Lattice Nexus-based FPGAs

    演示

    PCIe Colorbar Demo for Lattice Nexus-based FPGAs

    PCIe Colorbar Demo displays a series of moving colorbars by streaming the image data using DMA transfers from the FPGA to the host system.
    PCIe Colorbar Demo for Lattice Nexus-based FPGAs
  • PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

    演示

    PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

    The PCI Express DMA Throughput Demo allows to initiate DMA read and write transactions, transferring data from the host to the FPGA and vice versa.
    PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs
  • PCIe Multifunction Demo for Lattice Nexus-based FPGAs

    演示

    PCIe Multifunction Demo for Lattice Nexus-based FPGAs

    Demonstrates the multifunction capabilities of the Crosslink-NX FPGA that allows access to GPIO, MDIO and I2C registers.
    PCIe Multifunction Demo for Lattice Nexus-based FPGAs
  • 用户追踪和旁观者检测演示

    演示

    用户追踪和旁观者检测演示

    该演示示例使用CNN模型,在低功耗通用FPGA上运行,可检测和追踪多个人脸
    用户追踪和旁观者检测演示
  • 目标分类参考设计

    Reference Design

    目标分类参考设计

    基于在莱迪思CertusPro-NX低功耗FPGA上运行的Mobilenet神经网络模型实现目标分类参考设计
    目标分类参考设计
  • CrossLink-NX-33 Voice and Vision Machine Learning Board

    Board

    CrossLink-NX-33 Voice and Vision Machine Learning Board

    CrossLink-NX-33 Voice and Vision Machine Learning Board is designed using Crosslink-NX 33K, ideal for machine learning applications.
    CrossLink-NX-33 Voice and Vision Machine Learning Board
  • CrossLink-NX声音和视觉机器学习板

    Board

    CrossLink-NX声音和视觉机器学习板

    专为采用莱迪思sensAI和CrossLink-NX器件的低功耗机器学习应用而设计。包括图像传感器、麦克风、HyperRAM和扩展端口。
    CrossLink-NX声音和视觉机器学习板
  • RISC-V MC CPU IP核

    IP Core

    RISC-V MC CPU IP核

    Propel IP模块:具有可选的定时器和PIC子模块的32位RISC-V处理器核,通过AHB-Lite总线连接到其他Propel各类IP模块。
    RISC-V MC CPU IP核
  • RISC-V RX CPU IP Core

    IP Core

    RISC-V RX CPU IP Core

    Lattice RISC-V RX IP processes data and instructions while monitoring the external interrupts, using 32-bit RISC-V processor core and several submodules.
    RISC-V RX CPU IP Core
  • RISC-V SM CPU IP核

    IP Core

    RISC-V SM CPU IP核

    RISC-V SM CPU IP可以在处理数据和指令时处理外部中断。该IP支持RV32I指令集、外部中断和调试,遵循JTAG – IEEE 1149.1标准。
    RISC-V SM CPU IP核
  • Tightly-Coupled Memory (TCM) IP Core

    IP Core

    Tightly-Coupled Memory (TCM) IP Core

    The Tightly-Coupled Memory IP ensures low-latency automatic selection of the best memory type for user-selected application.
    Tightly-Coupled Memory (TCM) IP Core
  • CrossLink-NX VIP传感器输入板

    Board

    CrossLink-NX VIP传感器输入板

    Intended for use with the Lattice Embedded Vision Development Kit. Includes 4 camera inputs and HyperRam for embedded video applications with CrossLink-NX
    VIP 
    CrossLink-NX VIP传感器输入板
  • CrossLink-NX评估板

    Board

    CrossLink-NX评估板

    CrossLink-NX评估板载有一片40K逻辑单元的CrossLink-NX FPGA;可轻松访问FPGA上的大多数I/O和PCIe 5G SERDES; 拥有FPGA中间层板卡(FMC)、Raspberry Pi、MIPI CSI-2、D-PHY和通用接头,大大扩展了易用性。
    CrossLink-NX评估板
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