莱迪思解决方案

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  • Scene Segmentation Reference Design

    Reference Design

    Scene Segmentation Reference Design

    Efficient and low power approach for implementing scene segmentation using Lattice CrossLink-NX FPGA
    Scene Segmentation Reference Design
  • Crosslink-NX PCIe桥接板上的PCIe基础演示

    Demo

    Crosslink-NX PCIe桥接板上的PCIe基础演示

    该PCIe基础演示可以控制三个7段LED,并通过PCIe插槽操作FPGA的片上存储器。
    Crosslink-NX PCIe桥接板上的PCIe基础演示
  • PCIe Colorbar Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe Colorbar Demo for Lattice Nexus-based FPGAs

    Demo that displays a series of moving colorbars by streaming the image data using DMA transfers from the FPGA to the host system.
    PCIe Colorbar Demo for Lattice Nexus-based FPGAs
  • PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

    The PCI Express DMA Throughput Demo allows to initiate DMA read and write transactions, transferring data from the host to the FPGA and vice versa.
    PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs
  • PCIe Multifunction Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe Multifunction Demo for Lattice Nexus-based FPGAs

    Demonstrates the multifunction capabilities of the Crosslink-NX FPGA that allows access to GPIO, MDIO and I2C registers.
    PCIe Multifunction Demo for Lattice Nexus-based FPGAs
  • 用户追踪和旁观者检测演示

    Demo

    用户追踪和旁观者检测演示

    该演示示例使用CNN模型,在低功耗通用FPGA上运行,可检测和追踪多个人脸
    用户追踪和旁观者检测演示
  • CrossLink-NX-33 Voice and Vision Machine Learning Board

    Board

    CrossLink-NX-33 Voice and Vision Machine Learning Board

    Designed for low-power machine learning applications with Lattice sensAI and CrossLink-NX-33. Includes expansion ports and audio-based AI applications tools.
    CrossLink-NX-33 Voice and Vision Machine Learning Board
  • CrossLink-NX声音和视觉机器学习板

    Board

    CrossLink-NX声音和视觉机器学习板

    专为采用莱迪思sensAI和CrossLink-NX器件的低功耗机器学习应用而设计。包括图像传感器、麦克风、HyperRAM和扩展端口。
    CrossLink-NX声音和视觉机器学习板
  • Timer/Counter IP Core

    IP Core

    Timer/Counter IP Core

    Timer/Counter IP used to track timeouts in the system. Target devices are Certus-NX and Crosslink-NX.
    Timer/Counter IP Core
  • RISC-V MC CPU IP核

    IP Core

    RISC-V MC CPU IP核

    Propel IP模块:具有可选的定时器和PIC子模块的32位RISC-V处理器核,通过AHB-Lite总线连接到其他Propel各类IP模块。
    RISC-V MC CPU IP核
  • CrossLink-NX VIP传感器输入板

    Board

    CrossLink-NX VIP传感器输入板

    Intended for use with the Lattice Embedded Vision Development Kit. Includes 4 camera inputs and HyperRam for embedded video applications with CrossLink-NX
    VIP 
    CrossLink-NX VIP传感器输入板
  • CrossLink-NX评估板

    Board

    CrossLink-NX评估板

    CrossLink-NX评估板载有一片40K逻辑单元的CrossLink-NX FPGA;可轻松访问FPGA上的大多数I/O和PCIe 5G SERDES; 拥有FPGA中间层板卡(FMC)、Raspberry Pi、MIPI CSI-2、D-PHY和通用接头,大大扩展了易用性。
    CrossLink-NX评估板
  • PCI Express x1 & x4 IP Core for Nexus-based FPGAs

    IP Core

    PCI Express x1 & x4 IP Core for Nexus-based FPGAs

    The Lattice PCIe IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    PCI Express x1 & x4 IP Core for Nexus-based FPGAs
  • USB3-GbE VIP IO开发板

    Board

    USB3-GbE VIP IO开发板

    适用于视频接口平台(VIP)的USB 3.0 和千兆以太网输出板
    USB3-GbE VIP IO开发板
  • User Background Blurring Demonstration

    Demo

    User Background Blurring Demonstration

    Efficient and low power approach for implementing user background blurring using Lattice CrossLink-NX FPGA
    User Background Blurring Demonstration
  • 人脸识别参考设计

    Reference Design

    人脸识别参考设计

    在ECP5 FPGA上使用卷积神经网络检测人脸,并与已注册的人脸进行匹配。可以用于识别其他任何对象。
    人脸识别参考设计
  • 对象计数

    Reference Design

    对象计数

    基于莱迪思sensAI的对象计数应用示例。包括SPI、DDR IP模块、ISP引擎、8个CNN引擎和一个计数/标记叠加(overlay)引擎。
    对象计数
  • CNN Plus加速器IP

    IP Core

    CNN Plus加速器IP

    使用CNN实现超低功耗AI解决方案。最多可配置16位位宽。可搭配莱迪思神经网络编译器软件工具。
    CNN Plus加速器IP
  • Helion IONOS图像信号处理IP系列

    IP Core

    Helion IONOS图像信号处理IP系列

    来自Helion Vision的全面、高质量、可自行配置的ISP解决方案,包括了从基本到高级的高动态范围成像(HDRI)色彩流水线。
    Helion IONOS图像信号处理IP系列
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