莱迪思解决方案

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  • Secure Connected Motion Control Platform

    Reference Design

    Secure Connected Motion Control Platform

    ​​This platform offers resilient connectivity, low power consumption, high performance, and robust security is increasing across various industries.​
    Secure Connected Motion Control Platform
  • 拥有故障记录功能的电源时序演示

    演示

    拥有故障记录功能的电源时序演示

    使用L-ASC10监视和控制来自中心控制点的四个独立电源平面。带时间戳的故障记录。可扩展。
    拥有故障记录功能的电源时序演示
  • 莱迪思Sentry MachXO3D可信根演示

    演示

    莱迪思Sentry MachXO3D可信根演示

    完整的位流/固件包可帮助您在采用MachXO3D的莱迪思Sentry演示板上演示和测试符合NIST 800-193规范的PFR解决方案
    莱迪思Sentry MachXO3D可信根演示
  • ​​eSPI Target IP核​

    IP Core

    ​​eSPI Target IP核​

    莱迪思eSPI Target IP核符合英特尔eSPI规范,且在用户界面中拥有自己的虚拟线通道。
    ​​eSPI Target IP核​
  • RISC-V MC CPU IP核

    IP Core

    RISC-V MC CPU IP核

    Propel IP模块:具有可选的定时器和PIC子模块的32位RISC-V处理器核,通过AHB-Lite总线连接到其他Propel各类IP模块。
    RISC-V MC CPU IP核
  • RISC-V SM CPU IP核

    IP Core

    RISC-V SM CPU IP核

    RISC-V SM CPU IP可以在处理数据和指令时处理外部中断。该IP支持RV32I指令集、外部中断和调试,遵循JTAG – IEEE 1149.1标准。
    RISC-V SM CPU IP核
  • Lattice Sentry SMBus Mailbox IP Core

    IP Core

    Lattice Sentry SMBus Mailbox IP Core

    SMBus, a two-wire interface that support fairness arbitration and compatible with AHB-Lite specification. Target devices are Mach-NX and MachXO3D.
    Lattice Sentry SMBus Mailbox IP Core
  • 莱迪思Sentry MachXO3D演示板

    Board

    莱迪思Sentry MachXO3D演示板

    完善的平台来帮助您开发和测试符合NIST 800-193规范的PFR解决方案。包括众多特性以实现调试、接口和扩展
    莱迪思Sentry MachXO3D演示板
  • Lattice Sentry I2C Filter IP Core

    IP Core

    Lattice Sentry I2C Filter IP Core

    Sentry I2C Filter IP Core provides an interface between I2C bus devices and a host processor while protecting against common I2C bus vulnerabilities.
    Lattice Sentry I2C Filter IP Core
  • 莱迪思Sentry ESB Mux IP核用于MachXO3D

    IP Core

    莱迪思Sentry ESB Mux IP核用于MachXO3D

    用于莱迪思Sentry的Propel IP模块:访问MachXO3D的嵌入式安全模块(ESB)的同时进行内部加密操作
    莱迪思Sentry ESB Mux IP核用于MachXO3D
  • 莱迪思Sentry I2C监视器IP核用于MachXO3D

    IP Core

    莱迪思Sentry I2C监视器IP核用于MachXO3D

    用于莱迪思Sentry的Propel IP模块:监视I2C总线上的通信,识别和阻止潜在的非法通信。
    莱迪思Sentry I2C监视器IP核用于MachXO3D
  • 莱迪思Sentry QSPI Streamer IP核用于MachXO3D

    IP Core

    莱迪思Sentry QSPI Streamer IP核用于MachXO3D

    用于莱迪思Sentry的Propel IP模块:提供高速SPI存储器访问便于可信根平台操作中的固件身份验证
    莱迪思Sentry QSPI Streamer IP核用于MachXO3D
  • 莱迪思Sentry QSPI监视器IP核用于MachXO3D

    IP Core

    莱迪思Sentry QSPI监视器IP核用于MachXO3D

    用于莱迪思Sentry的Propel IP模块:监视SPI/QSPI总线上的通信,可识别和阻止潜在的非法通信。
    莱迪思Sentry QSPI监视器IP核用于MachXO3D
  • ​​M-PESTI Initiator IP核

    IP Core

    ​​M-PESTI Initiator IP核

    莱迪思M-PESTI IP核可在系统启动前检测外设存在和属性采集。
    ​​M-PESTI Initiator IP核
  • Lattice Sentry 4.0 SCM和HPM CPLD参考设计

    Reference Design

    Lattice Sentry 4.0 SCM和HPM CPLD参考设计

    这是一个Sentry 4.0服务器解决方案平台的安全控制模块(SCM)和主机平台模块(HPM)的CPLD设计模板。
    Lattice Sentry 4.0 SCM和HPM CPLD参考设计
  • MPESTI Initiator Reference Design

    Reference Design

    MPESTI Initiator Reference Design

    MPESTI Initiator Reference Design provides the solution template which is compliant with the MPESTI Base Specification.
    MPESTI Initiator Reference Design
  • APB to AHB-Lite Bridge Reference Design

    Reference Design

    APB to AHB-Lite Bridge Reference Design

    The APB to AHB-Lite Bridge Reference Design provides an interface between the low power APB and the high-speed AHB-Lite.
    APB to AHB-Lite Bridge Reference Design
  • DC-SCM LVDS Tunneling Protocol and Interface IP Core

    IP Core

    DC-SCM LVDS Tunneling Protocol and Interface IP Core

    LTPI IP Core is an Open Computer Project Data Center – Secure Control Module Standards compatible solution which is introduced in the DC-SCM 2.0 Specification.
    DC-SCM LVDS Tunneling Protocol and Interface IP Core
  • LVDS Tunneling Protocol and Interface Reference Design

    Reference Design

    LVDS Tunneling Protocol and Interface Reference Design

    The DC-SCM 2.0 LTPI Reference Design provides multiple solution compliant with DC-SCM 2.0 with a standardized DC-SCI and aggregating multiple data channels.
    LVDS Tunneling Protocol and Interface Reference Design
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