莱迪思解决方案

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  • FFT 编译器

    IP Core

    FFT 编译器

    The FFT Compiler IP Core can be configured to perform forward FFT, inverse FFT (IFFT), or port selectable forward/inverse FFT.
    FFT 编译器
  • FIR 滤波器生成器

    IP Core

    FIR 滤波器生成器

    可灵活配置的多通道FIR滤波器。最多支持256个通道,每个拥有2048个抽头。输入和系数宽度为4至32位。
    FIR 滤波器生成器
  • JESD204B IP核

    IP Core

    JESD204B IP核

    莱迪思JESD204B IP核是用于数据转换器和FPGA器件之间的高速串行接口,用于取代传统接口。
    JESD204B IP核
  • PCI Express x1、x4 Root Complex Lite IP核

    IP Core

    PCI Express x1、x4 Root Complex Lite IP核

    Provides a PCI Express x1 and x4 root complex solution from the electrical SERDES interface, physical layer, data link layer and a minimum transaction layer in PCIe protocol stack
    PCI Express x1、x4 Root Complex Lite IP核
  • ML-KEM-512/768/1024 (CRYSTALS-Kyber), Balanced (XIP6110B)

    IP Core

    ML-KEM-512/768/1024 (CRYSTALS-Kyber), Balanced (XIP6110B)

    ML-KEM-512/768/1024 is an IP core for post-quantum Key Encapsulation Mechanism (KEM), optimized for a good balance between speed and resource requirements.
    ML-KEM-512/768/1024 (CRYSTALS-Kyber), Balanced (XIP6110B)
  • 莱迪思图像信号处理演示

    演示

    莱迪思图像信号处理演示

    为嵌入式视觉开发套件提供基于ECP5 FPGA的完整ISP示例设计,非常适合工业、医疗和汽车应用。
    莱迪思图像信号处理演示
  • DDR3 Memory Interface Demonstration

    演示

    DDR3 Memory Interface Demonstration

    The Lattice DDR3 Memory Interface demonstrates the functionality of DDR3 SDRAM Controller IP at core speed of 400MHz and 800Mbps.
    DDR3 Memory Interface Demonstration
  • AXI4 to APB Bridge Module

    IP Core

    AXI4 to APB Bridge Module

    The Lattice Semiconductor AXI4 to APB Bridge Module provides an interface between the high-speed AXI4 and APB.
    AXI4 to APB Bridge Module
  • AXI4 to AHB-Lite Bridge Module

    IP Core

    AXI4 to AHB-Lite Bridge Module

    Lattice Semiconductor AXI4 to AHB-Lite Bridge Module provides an interface between the high-speed AXI4 and AHB-Lite.
    AXI4 to AHB-Lite Bridge Module
  • AHB-Lite to AXI4 Bridge IP Core

    IP Core

    AHB-Lite to AXI4 Bridge IP Core

    The Lattice AHB-Lite to AXI4 Bridge IP Core is used for interfacing one AHB-Lite Manager and one AXI4 Subordinate.
    AHB-Lite to AXI4 Bridge IP Core
  • AXI4 Interconnect Module

    IP Core

    AXI4 Interconnect Module

    AXI4 Interconnect is a flexible, versatile, and easy-to-use IP with high-performance and low-latency interconnect fabric for AMBA 4 AXI/AXI-lite based systems.
    AXI4 Interconnect Module
  • Lattice QSPI to NXP MPU Interface Reference Design

    Reference Design

    Lattice QSPI to NXP MPU Interface Reference Design

    This Lattice and NXP joint solution is designed to implement FlexSPI communication and expedite deployment using the Lattice ECP5 Evaluation Board.
    Lattice QSPI to NXP MPU Interface Reference Design
  • LimeSDR Mini Development Board by Lime Microsystems

    Board

    LimeSDR Mini Development Board by Lime Microsystems

    LimeSDR Mini Dev Board is a low cost, open source and apps-enabled SDR platform that can be used to support any type of wireless communication standard.
    LimeSDR Mini Development Board by Lime Microsystems
  • ECP5评估板

    Board

    ECP5评估板

    售价仅为99美元的ECP5评估板拥有一片85K LUT的ECP5-5G FPGA;可轻松访问大多数I/O以及SERDES;更支持Arduino和Raspberry Pi以及通用接口以提高可用性。
    ECP5评估板
  • USB3-GbE VIP IO开发板

    Board

    USB3-GbE VIP IO开发板

    适用于视频接口平台(VIP)的USB 3.0 和千兆以太网输出板
    USB3-GbE VIP IO开发板
  • JESD204 ADC参考设计

    Reference Design

    JESD204 ADC参考设计

    Provides designers an ideal platform for a low cost, low power and small footprint solution for FPGA based serial data acquisition and processing
    JESD204 ADC参考设计
  • 人脸识别参考设计

    Reference Design

    人脸识别参考设计

    在ECP5 FPGA上使用卷积神经网络检测人脸,并与已注册的人脸进行匹配。可以用于识别其他任何对象。
    人脸识别参考设计
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