莱迪思解决方案

IP Core

FFT 编译器

The FFT Compiler IP Core can be configured to perform forward FFT, inverse FFT (IFFT), or port selectable forward/inverse FFT.

ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, LatticeXP2, Certus-NX, CertusPro-NX, MachXO5-NX, CrossLink-NX, Avant-E, Avant-G, Avant-X 

Data Communication, DSP, Guidance Systems, Automotive, DSP Bundle, SDR 

IP Core

FIR 滤波器生成器

可灵活配置的多通道FIR滤波器。最多支持256个通道，每个拥有2048个抽头。输入和系数宽度为4至32位。

ECP5 / ECP5-5G, LatticeECP3, LatticeXP2, CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX, Avant-E, Avant-G, Avant-X 

DSP, Guidance Systems, Automotive, DSP Bundle, SDR 

IP Core

JESD204B IP核

莱迪思JESD204B IP核是用于数据转换器和FPGA器件之间的高速串行接口，用于取代传统接口。

ECP5 / ECP5-5G, LatticeECP3, CertusPro-NX 

ADC/DAC, DSP, SDR 

IP Core

10Gb Ethernet MAC+PHY IP Core

The Lattice 10G Ethernet (GbE) IP core supports the ability to transmit and receive data between a host processor and an Ethernet network.

Avant-G, Avant-X, CertusPro-NX 

Ethernet, PCS, XGMII, AXI4, Ethernet Bundle, SDR 

IP Core

25Gb以太网MAC+PHY IP核

莱迪思半导体的25G以太网（GbE）IP核支持在主机处理器和以太网网络之间发送和接收数据。

Avant-X 

Ethernet, Lattice Avant, IEEE 802.3, Ethernet Bundle, SDR 

IP Core

PCI Express x1、x4 Root Complex Lite IP核

Provides a PCI Express x1 and x4 root complex solution from the electrical SERDES interface, physical layer, data link layer and a minimum transaction layer in PCIe protocol stack

ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M 

PCIe, Guidance Systems, Automotive, PCIe Bundle, SDR 

IP Core

Image Signal Processing IP Cores Suite

The Lattice mVision ISP IP Core implements ISP pipelines for image quality enhancements in embedded designs based on Lattice FPGA devices.

CrossLink-NX, Certus-NX, CertusPro-NX, Avant-E 

AXI, AXI-Stream, AXI-Lite Interface, AWB, Camera, CCM, CFA Interpolation, Debayer, Image Processing, Image Signal Processing, Lattice mVision, RGB, Defense 

IP Core

MACsec AES256-GCM, High-speed (XIP1213H)

The high-speed MACsec IP core implements the MACsec protocol as standardized in IEEE 802.1AE-2018, defining a security infrastructure for OSI model Layer 2 traffic.

Avant-E, Avant-G, Avant-X 

AES, Encryption, NIST, Security, ECC, Public/Private Key, SHA, SDR 

IP Core

QSPI闪存控制器IP核

QSPI闪存控制器IP可以通过标准、扩展的双/四、双或四通道SPI协议与多个外部SPI闪存器件进行通信。

Avant-E, Avant-G, Avant-X, CertusPro-NX, Certus-NX 

QSPI, SPI Flash, SPI, Flash 

IP Core

USB 2.0/3.2 IP核

莱迪思USB 2.0/3.2 IP核提供了一种连接USB主机的解决方案，适用于莱迪思CrossLink-NX FPGA最新器件。

CrossLink-NX 

USB, USB2, USB3, AHB, AHB-L, AHB-Lite, AXI, I2C, SPI, JTAG, LVDS, SLVS, FTDI 

IP Core

ML-KEM-512/768/1024 (CRYSTALS-Kyber), Balanced (XIP6110B)

ML-KEM-512/768/1024 is an IP core for post-quantum Key Encapsulation Mechanism (KEM), optimized for a good balance between speed and resource requirements.

Avant-E, Avant-G, Avant-X, CertusPro-NX, ECP5 / ECP5-5G 

Encryption, NIST, Public/Private Key, Security, SDR 

IP Core

​​eSPI Target IP核​

莱迪思eSPI Target IP核符合英特尔eSPI规范，且在用户界面中拥有自己的虚拟线通道。

MachXO5-NX, Mach-NX, MachXO3D, MachXO3 

APB, AHB-Lite, Lattice Sentry 

IP Core

PCI Express for Nexus FPGAs

The Lattice PCIe IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.

CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX 

APB, AHB, AHB-Lite, RTL, PCI, PCIe, Bus Controllers, Defense, Automotive, PCIe Bundle, SDR 

IP Core

RISC-V MC CPU IP核

Propel IP模块：具有可选的定时器和PIC子模块的32位RISC-V处理器核，通过AHB-Lite总线连接到其他Propel各类IP模块。

MachXO3D, Certus-NX, CrossLink-NX, Avant-E, MachXO5-NX, CertusPro-NX, MachXO3, MachXO2 , Avant-G, Avant-X, ECP5 / ECP5-5G 

AHB-Lite, Soft Processor, RISC-V, Lattice Propel, TOR Switch, Defense, Automotive, SDR 

IP Core

RISC-V SM CPU IP核

RISC-V SM CPU IP可以在处理数据和指令时处理外部中断。该IP支持RV32I指令集、外部中断和调试，遵循JTAG – IEEE 1149.1标准。

Avant-E, MachXO5-NX, Certus-NX, CertusPro-NX, CrossLink-NX, MachXO3D, MachXO3, MachXO2 , Avant-G, Avant-X, ECP5 / ECP5-5G 

AHB-Lite, Soft Processor, RISC-V, Lattice Propel, TOR Switch, Defense, Automotive, SDR 

IP Core

PCI Express for Avant FPGAs

The Lattice PCIe X8 IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.

Avant-G, Avant-X 

AXI, AHB, AHB-Lite, RTL, PCIe, Bus Controllers, Defense, Automotive, Lattice Avant, PCI, PCIe Bundle, SDR 

IP Core

RISC-V RX CPU IP核

莱迪思RISC-V RX IP使用32位RISC-V处理器核和多个子模块，在监控外部中断的同时处理数据和指令。

Avant-E, MachXO5-NX, Certus-NX, CertusPro-NX, CrossLink-NX, Avant-G, Avant-X, ECP5 / ECP5-5G 

AHB-Lite, Soft Processor, RISC-V, RTOS, Lattice Propel, Defense, Automotive 

IP Core

Lattice Sentry PLD Interface IP Core

Lattice Semiconductor Customer Programmable Logic Devices (PLD)implements a bidirectional mailbox for sending and receiving messages.

Mach-NX, MachXO5-NX 

AHB-Lite, APB, FPGA, RTL, Lattice Propel, PLD, Lattice Sentry, Lattice Sentry PFR IP Package, Security 

IP Core

Lattice Sentry SMBus Mailbox IP Core

SMBus, a two-wire interface that support fairness arbitration and compatible with AHB-Lite specification. Target devices are Mach-NX and MachXO3D.

MachXO3D, Mach-NX 

I2C, AHB-L, Lattice Propel, Lattice Sentry, Security, SMBus, RoT, RTL, Lattice Sentry PFR IP Package 

IP Core

PIC IP Core

Lattice Semiconductor PIC soft IP with configurable 1~8 interrupt inputs and 32-bit AHB-L interface for Mach-NX FPGA

Mach-NX, MachXO5-NX 

AHB-Lite, Lattice Propel, Lattice Diamond, Lattice Sentry, Lattice Sentry PFR IP Package, Security