莱迪思解决方案

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  • 10Gb Ethernet MAC+PHY IP Core

    IP Core

    10Gb Ethernet MAC+PHY IP Core

    The Lattice 10G Ethernet (GbE) IP core supports the ability to transmit and receive data between a host processor and an Ethernet network.
    10Gb Ethernet MAC+PHY IP Core
  • 25Gb以太网MAC+PHY IP核

    IP Core

    25Gb以太网MAC+PHY IP核

    莱迪思半导体的25G以太网(GbE)IP核支持在主机处理器和以太网网络之间发送和接收数据。
    25Gb以太网MAC+PHY IP核
  • PCI Express for Avant FPGAs

    IP Core

    PCI Express for Avant FPGAs

    The Lattice PCIe X8 IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    PCI Express for Avant FPGAs
  • QSPI闪存控制器IP核

    IP Core

    QSPI闪存控制器IP核

    QSPI闪存控制器IP可以通过标准、扩展的双/四、双或四通道SPI协议与多个外部SPI闪存器件进行通信。
  • USB 2.0/3.2 IP核

    IP Core

    USB 2.0/3.2 IP核

    莱迪思USB 2.0/3.2 IP核提供了一种连接USB主机的解决方案,适用于莱迪思CrossLink-NX FPGA最新器件。
    USB 2.0/3.2 IP核
  • RISC-V MC CPU IP核

    IP Core

    RISC-V MC CPU IP核

    Propel IP模块:具有可选的定时器和PIC子模块的32位RISC-V处理器核,通过AHB-Lite总线连接到其他Propel各类IP模块。
    RISC-V MC CPU IP核
  • RISC-V RX CPU IP Core

    IP Core

    RISC-V RX CPU IP Core

    Lattice RISC-V RX IP processes data and instructions while monitoring the external interrupts, using 32-bit RISC-V processor core and several submodules.
    RISC-V RX CPU IP Core
  • RISC-V SM CPU IP核

    IP Core

    RISC-V SM CPU IP核

    RISC-V SM CPU IP可以在处理数据和指令时处理外部中断。该IP支持RV32I指令集、外部中断和调试,遵循JTAG – IEEE 1149.1标准。
    RISC-V SM CPU IP核
  • Tightly-Coupled Memory (TCM) IP Core

    IP Core

    Tightly-Coupled Memory (TCM) IP Core

    The Tightly-Coupled Memory IP ensures low-latency automatic selection of the best memory type for user-selected application.
    Tightly-Coupled Memory (TCM) IP Core
  • Lattice Sentry I2C Filter IP Core

    IP Core

    Lattice Sentry I2C Filter IP Core

    Sentry I2C Filter IP Core provides an interface between I2C bus devices and a host processor while protecting against common I2C bus vulnerabilities.
    Lattice Sentry I2C Filter IP Core
  • Lattice Sentry PLD Interface IP Core

    IP Core

    Lattice Sentry PLD Interface IP Core

    Lattice Semiconductor Customer Programmable Logic Devices (PLD)implements a bidirectional mailbox for sending and receiving messages.
    Lattice Sentry PLD Interface IP Core
  • Lattice Sentry SMBus Mailbox IP Core

    IP Core

    Lattice Sentry SMBus Mailbox IP Core

    SMBus, a two-wire interface that support fairness arbitration and compatible with AHB-Lite specification. Target devices are Mach-NX and MachXO3D.
    Lattice Sentry SMBus Mailbox IP Core
  • PIC IP Core

    IP Core

    PIC IP Core

    Lattice Semiconductor PIC soft IP with configurable 1~8 interrupt inputs and 32-bit AHB-L interface for Mach-NX FPGA
    PIC IP Core
  • SFB Interface IP Core

    IP Core

    SFB Interface IP Core

    SFB allow access to AHB-L CPLD block , management CPU recovery circuit and Flash sector for read/write.
    SFB Interface IP Core
  • 莱迪思Sentry ESB Mux IP核用于MachXO3D

    IP Core

    莱迪思Sentry ESB Mux IP核用于MachXO3D

    用于莱迪思Sentry的Propel IP模块:访问MachXO3D的嵌入式安全模块(ESB)的同时进行内部加密操作
    莱迪思Sentry ESB Mux IP核用于MachXO3D
  • 莱迪思Sentry I2C监视器IP核用于MachXO3D

    IP Core

    莱迪思Sentry I2C监视器IP核用于MachXO3D

    用于莱迪思Sentry的Propel IP模块:监视I2C总线上的通信,识别和阻止潜在的非法通信。
    莱迪思Sentry I2C监视器IP核用于MachXO3D
  • 莱迪思Sentry QSPI Streamer IP核用于MachXO3D

    IP Core

    莱迪思Sentry QSPI Streamer IP核用于MachXO3D

    用于莱迪思Sentry的Propel IP模块:提供高速SPI存储器访问便于可信根平台操作中的固件身份验证
    莱迪思Sentry QSPI Streamer IP核用于MachXO3D
  • 莱迪思Sentry QSPI监视器IP核用于MachXO3D

    IP Core

    莱迪思Sentry QSPI监视器IP核用于MachXO3D

    用于莱迪思Sentry的Propel IP模块:监视SPI/QSPI总线上的通信,可识别和阻止潜在的非法通信。
    莱迪思Sentry QSPI监视器IP核用于MachXO3D
  • AHB-Lite to AXI4 Bridge IP Core

    IP Core

    AHB-Lite to AXI4 Bridge IP Core

    The Lattice AHB-Lite to AXI4 Bridge IP Core is used for interfacing one AHB-Lite Manager and one AXI4 Subordinate.
    AHB-Lite to AXI4 Bridge IP Core
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