莱迪思解决方案

这里有轻松快速实现设计所需的全部资源

Share This Result >

Narrow Your Results



Solution Type



Device Support




















Tags
















































































































































































Providers


























Clear All
  • USB 2.0/3.2 IP核

    IP Core

    USB 2.0/3.2 IP核

    莱迪思USB 2.0/3.2 IP核提供了一种连接USB主机的解决方案,适用于莱迪思CrossLink-NX FPGA最新器件。
    USB 2.0/3.2 IP核
  • RISC-V MC CPU IP核

    IP Core

    RISC-V MC CPU IP核

    Propel IP模块:具有可选的定时器和PIC子模块的32位RISC-V处理器核,通过AHB-Lite总线连接到其他Propel各类IP模块。
    RISC-V MC CPU IP核
  • RISC-V RX CPU IP Core

    IP Core

    RISC-V RX CPU IP Core

    Lattice RISC-V RX IP processes data and instructions while monitoring the external interrupts, using 32-bit RISC-V processor core and several submodules.
    RISC-V RX CPU IP Core
  • RISC-V SM CPU IP核

    IP Core

    RISC-V SM CPU IP核

    RISC-V SM CPU IP可以在处理数据和指令时处理外部中断。该IP支持RV32I指令集、外部中断和调试,遵循JTAG – IEEE 1149.1标准。
    RISC-V SM CPU IP核
  • Tightly-Coupled Memory (TCM) IP Core

    IP Core

    Tightly-Coupled Memory (TCM) IP Core

    The Tightly-Coupled Memory IP ensures low-latency automatic selection of the best memory type for user-selected application.
    Tightly-Coupled Memory (TCM) IP Core
  • Lattice Sentry I2C Filter IP Core

    IP Core

    Lattice Sentry I2C Filter IP Core

    Sentry I2C Filter IP Core provides an interface between I2C bus devices and a host processor while protecting against common I2C bus vulnerabilities.
    Lattice Sentry I2C Filter IP Core
  • Lattice Sentry PLD Interface IP Core

    IP Core

    Lattice Sentry PLD Interface IP Core

    Lattice Semiconductor Customer Programmable Logic Devices (PLD)implements a bidirectional mailbox for sending and receiving messages.
    Lattice Sentry PLD Interface IP Core
  • Lattice Sentry SMBus Mailbox IP Core

    IP Core

    Lattice Sentry SMBus Mailbox IP Core

    SMBus, a two-wire interface that support fairness arbitration and compatible with AHB-Lite specification. Target devices are Mach-NX and MachXO3D.
    Lattice Sentry SMBus Mailbox IP Core
  • PIC IP Core

    IP Core

    PIC IP Core

    Lattice Semiconductor PIC soft IP with configurable 1~8 interrupt inputs and 32-bit AHB-L interface for Mach-NX FPGA
    PIC IP Core
  • SFB Interface IP Core

    IP Core

    SFB Interface IP Core

    SFB allow access to AHB-L CPLD block , management CPU recovery circuit and Flash sector for read/write.
    SFB Interface IP Core
  • Timer/Counter IP Core

    IP Core

    Timer/Counter IP Core

    Timer/Counter IP used to track timeouts in the system. Target devices are Certus-NX and Crosslink-NX.
    Timer/Counter IP Core
  • 莱迪思Sentry ESB Mux IP核用于MachXO3D

    IP Core

    莱迪思Sentry ESB Mux IP核用于MachXO3D

    用于莱迪思Sentry的Propel IP模块:访问MachXO3D的嵌入式安全模块(ESB)的同时进行内部加密操作
    莱迪思Sentry ESB Mux IP核用于MachXO3D
  • 莱迪思Sentry I2C监视器IP核用于MachXO3D

    IP Core

    莱迪思Sentry I2C监视器IP核用于MachXO3D

    用于莱迪思Sentry的Propel IP模块:监视I2C总线上的通信,识别和阻止潜在的非法通信。
    莱迪思Sentry I2C监视器IP核用于MachXO3D
  • 莱迪思Sentry QSPI Streamer IP核用于MachXO3D

    IP Core

    莱迪思Sentry QSPI Streamer IP核用于MachXO3D

    用于莱迪思Sentry的Propel IP模块:提供高速SPI存储器访问便于可信根平台操作中的固件身份验证
    莱迪思Sentry QSPI Streamer IP核用于MachXO3D
  • 莱迪思Sentry QSPI监视器IP核用于MachXO3D

    IP Core

    莱迪思Sentry QSPI监视器IP核用于MachXO3D

    用于莱迪思Sentry的Propel IP模块:监视SPI/QSPI总线上的通信,可识别和阻止潜在的非法通信。
    莱迪思Sentry QSPI监视器IP核用于MachXO3D
  • DisplayPort IP核

    IP Core

    DisplayPort IP核

    莱迪思DisplayPort IP核用于传输和接收消费类和专业显示器的串行数字视频。
    DisplayPort IP核
  • Image Signal Processing IP Cores Suite

    IP Core

    Image Signal Processing IP Cores Suite

    The Lattice mVision ISP IP Core implements ISP pipelines for image quality enhancements in embedded designs based on Lattice FPGA devices.
    Image Signal Processing IP Cores Suite
  • PCI Express x1 & x4 IP Core for Nexus-based FPGAs

    IP Core

    PCI Express x1 & x4 IP Core for Nexus-based FPGAs

    The Lattice PCIe IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    PCI Express x1 & x4 IP Core for Nexus-based FPGAs
  • 视频缩放器IP核

    IP Core

    视频缩放器IP核

    莱迪思视频缩放器IP核用于放大或缩小视频流的分辨率。
    视频缩放器IP核
  • 高级CNN加速器IP

    IP Core

    高级CNN加速器IP

    计算神经网络的各个网络层,包括卷积层、池化层、批量归一化层和全连接层。
    高级CNN加速器IP
  • Page 1 of 15
    First Previous
    1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
    Next Last