The Lattice Semiconductor JTAG Bridge IP provides an efficient solution for debugging on-board issues by allowing you to access memory and peripheral registers directly using this IP, without involving the processor. It converts Joint Test Action Group (JTAG) Test Access Port (TAP) signals into Advanced eXtensible Interface 4 (AXI4) transactions, enabling you to perform read and write operations with byte, half-word, or word lengths.
Resource Utilization details are available in the IP Core User Guide.