The Lattice Semiconductor AHB-Lite Manager Bus Functional Model (BFM) Lite Verification IP (VIP) is intended for simulation and verification use only. It supports the generation of various AHB-Lite transaction types, including single, pipelined, and burst transactions.
The AHB-Lite Manager BFM Lite VIP design is implemented in SystemVerilog and can be instantiated in the Lattice Propel™ Builder software. Refer to the user guide for more detail on the implementation.
Features
- Support AHB-Lite manager interface
- Simple API for transaction generation
- Supported transaction generation
- Single read and write
- Pipelined read and write
- Burst read and write
