AES256-GCM, High-speed (XIP1113H)

XIP1113H – Advanced Encryption Standard (256-bit key), Galois Counter Mode IP Core


The high-throughput AES256-GCM from Xiphera implements the Advanced Encryption Standard (AES) in Galois Counter Mode (GCM). AES-GCM is a widely used cryptographic algorithm for Authenticated Enryption with Associated Data (AEAD) purposes, as it provides both data confidentiality and authenticity.

Performance: The IP core achieves a throughput in the Gbps range, for example 15.92+ Gbps in Lattice ECP5.

Standard Compliance: The IP core is fully compliant with both the Advanced Encryption Algorithm (AES) standard and the Galois Counter Mode (GCM) standard.

Moderate Resource Requirements: The entire IP core requires 49516 Lookup Tables (4LUTs) (Lattice® ECP5®), and does not require any multipliers, DSPBlocks or internal memory in a typical Lattice FPGA implementation.


  • 128-bit and 256-bit Interfaces ease the integration of the high-speed AES-GCM with other high-speed FPGA logic.
  • Optimized Implementation utilising unrolling, pipelining, optimized AES S-box design, and GMAC calculation based on pipelined Karatsuba multipliers enable extremely high performance.

Block Diagram

Ordering Information

Please contact for pricing and your preferred delivery method. The IP core can be shipped in a number of formats, including netlist, source code, or encrypted source code. Additionally, a comprehensive VHDL testbench and a detailed datasheet are included.

Download the full product brief:


标题 编号 版本 日期 格式 文件大小
Xiphera Lattice IP Core Metrics
1.0 8/5/2021 PDF 41.2 KB