XIP1111H: AES128-GCM High-Speed IP Core

High-speed IP core implementing AES128 in GCM mode of operation

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AES Galois Counter Mode (GCM) is a popular Authenticated Encryption with Associated Data (AEAD) cipher and its example use cases include securing TLS traffic.

Easy integration with other FPGA logic, as the functionality of XIP1111H does not rely on any FPGA family specific features.

Features

  • Moderate resource requirements: The entire XIP1111H requires 38145 Lookup Tables (4LUTs) (Lattice ECP5), and does not require any multipliers, DSPBlocks or internal memory in a typical FPGA implementation.
  • Optimized Implementation utilizing unrolling, pipelining, optimized AES S-box design, and GMAC calculation based on pipelined Karatsuba multipliers enable extremely high performance.
  • Performance: XIP1111H achieves a throughput in the Gbps range, for example 15.25+ Gbps in Lattice ECP5.
  • Standard Compliance: XIP1111H is fully compliant with both the Advanced Encryption Algorithm (AES) standard FIPS-197 as well as with the Galois Counter Mode (GCM) standard SP 800-38D.

Block Diagram

Internal high-level block diagram of XIP1111H放大图片

Resource Usage and Performance

FPGA family Resources fMAX Max. Throughput
Lattice ECP5 38145 4LUTs 119.10 MHz 15.25 Gbps

Resource usage and performance of XIP1111H on Lattice ECP5 FPGA family. On request, the resource estimates can also be supplied for other Lattice FPGA families.

Ordering Information

Please contact sales@xiphera.com for pricing and your preferred delivery method. XIP1111H can be shipped in a number of formats, including netlist, source code, or encrypted source code. Additionally, a comprehensive VHDL testbench and a detailed datasheet are included.

You can download the Lattice Product Brief from https://xiphera.com/partners/lattice/XIP1111H_PB_lattice.pdf

Documentation

资讯资源
标题 编号 版本 日期 格式 文件大小
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Xiphera Lattice IP Core Metrics
1.0 8/5/2021 PDF 41.2 KB

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