PCI Express for Avant FPGAs

The Hard IP PHY key features include:

• Aggregation and bifurcation up to x4 lanes and x8 lanes PHY configuration
• Data rates of 2.5 Gbps, 5.0 Gbps, 8.0 Gbps, and 16.0 Gbps
• Selectable parallel data widths such as 8, 16, 32, 64
• 8b/10b encoding at 2.5 Gbps and 5 Gbps, and 128b/130b encoding at 8 Gbps and 16 Gbps

The Hard IP Link Layer key features include:

• PCI Express Base Specification Revision 4.0 compliant including compliance with earlier PCI Express Specifications.
• Backward compatible with PCI Express 3.x, 2.x, 1.x
• x8 PCI Express Lanes with support for bifurcation. Supported lane configurations:
  • Radiant 2023.2 – 1 × 4, 1 × 2, 1 × 1
  • Radiant 2024.1 and future Radiant releases – 1 × 8, 1 × 4, 1 × 2, 1 × 1
• 16.0GT/s, 8.0GT/s, 5.0 GT/s, and 2.5 GT/s line rate support

The Soft IP features include:

• TLP Data Interface
• AXI4-Stream Data Interface Option
• LMMI Register Interfaces
• AXI-L Register Interface

The software driver is developed using Jungo WinDriver Software toolkit. You can develop your own driver or use the Jungo WinDriver for driver development. To use Jungo WinDriver, contact Jungo to obtain a valid paid annual subscription.

For more information, please contact through this link: WinDriver of Jungo (or email at: WinDriver@jungo.com )