Memory Controller IP Core

Supports LPDDR4, compliant to JESD209-4 SDRAM Standard

The Lattice Semiconductor Memory Controller Interface module provides a solution to interface to LPDDR4 DDR memory standards. Lattice provides a turnkey solution with controller, DDR PHY, the associated clocking scheme and training related logic.

The Lattice Memory Controller IP supports JEDEC compliant JESD209-4C LPDDR4 standard.

The Memory Controller IP reduces the effort required to integrate the LPDDR4 memory controller with the user application design and minimizes the need to directly deal with the LPDDR4 memory interface by providing AHB-L standard interface or Native Interface.

Features

  • Memory Controller supports LPDDR4, compliant to JESD209-4 SDRAM standard
  • Speeds of up to 533 MHz command or data speeds of 1066 MTps
  • Configurable address widths to support various memory densities
  • DDR widths of x16, x32, and x64
  • Burst length BL16/32 OTF

Jump to

Block Diagram

Ordering Information

Family License Type Ordering Part Number
CertusPro-NX Single-Design License LPDDR4-MC-CPNX-U
Multi-Site License LPDDR4-MC-CPNX-UT

Documentation

快速参考
标题 编号 版本 日期 格式 文件大小
选择全部
Memory Controller IP Core - Lattice Radiant Software
FPGA-IPUG-02127 1.3 2/23/2022 PDF 1.7 MB
Memory Modules - Lattice Radiant Software
FPGA-IPUG-02033 2.5 6/23/2021 PDF 2.4 MB