Serial RapidIO - Physical Layer Interface


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The Serial RapidIO core supports the physical layer specification as defined in the RapidIO Specification Rev 1.2. The Serial RapidIO Physical Layer defines a protocol for packet delivery between Serial RapidIO devices and other devices, including packet transmission, flow control, error management and link maintenance protocols. The core supports one-lane high speed (1x mode) running at 1.0, 2.0 Gbps or a maximum of 2.5 Gbps. This Serial RapidIO core is optimized to support ORT82G5/ORT42G5 FPSCs.

    Features

    • Supports High Speed 1x Mode (up to 2.5 Gbps)
    • 8B/10B Encoding and Decoding
    • Clock and Data Recovery (CDR)
    • Lane Synchronization
    • CRC Generation and Checking
    • Error Detection
    • Packet/Control Symbol Assembly and De-assembly
    • Simple User Interface for Easy Integration into User Logic
    • Targets ORT82G5/ORT42G5 FPSC

    Jump to

    Block Diagram

    SerialRapid IO Block Diagram

    Performance and Size

    Performance and Utilization for ORCA 41
    Name of Parameter File rio_seri_t42g5_1_001.lpc
    ORCA 42 PFUs 996
    LUTs2 4386
    Registers2 4232
    EBR 23
    PIO2 178
    fMAX sys_clk and
    pmi_usr_clk (MHz)    		 39.0625

    1 Performance and utilization characteristics are generated using an ORT42G5-2BM484 in Lattice’s ispLEVER v.3.1 software. When using this IP core in a different density, package, speed, or grade within ORCA 4 family, performance and utilization may vary.
    2 Performance and utilization characteristics are counted based on the utilization of the top level module which includes rios_smi module.

    Ordering Infomation

    • Ordering Part Number: RIO-SERI-T42G5-N1
    • To find out how to purchase the 32 Bit PCI Target IP Core, please contact your local Lattice Sales Office.

    Documentation

    快速参考
    资讯资源
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    标题编号版本日期格式文件大小
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    Serial RapidIO User's Guide
    		11/1/2005PDF892.4 KB
    标题编号版本日期格式文件大小
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    IP Module Evaluation Tutorial
    		8/1/2004PDF216.1 KB
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    Simulation model (no-debug version) for FPSC System bus
    This is a 'no debug' version of the ModelSIM FPSC device model. This model may be required to simulate some Lattice IP cores with Lattice FPSC devices.    		2/1/2004ZIP4.4 MB
    Simulation model (no-debug version) for ORSO82G5/ORSO42G5
    This is a 'no debug' version of the ModelSIM FPSC device model. This model may be required to simulate some Lattice IP cores with the ORSO82G5 or ORSO42G5 devices.    		2/1/2004ZIP1.8 MB
    Simulation model (no-debug version) for ORT82G5/ORT42G5
    This is a 'no debug' version of the ModelSIM FPSC device model. This model may be required to simulate some Lattice IP cores with the ORT82G5 or ORT42G5 devices.    		2/1/2004ZIP1.9 MB
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    Evaluation Package for Serial RapidIO for ORCA 4
    		2/1/2004ZIP1.7 MB