EP300: PowerPC 总线仲裁器

EP300 PowerPC总线仲裁器为直接仲裁连接到PowerPC主机总线的多个总线主设备提供了所有必要的功能。仲裁器支持独立的地址和数据总线,通过PowerPC总线架构实现了高性能。为总线上的每个主设备提供独立的地址总线授权和数据总线授权信号。仲裁器采用先进的内置状态机来协调的地址总线和数据总线。在任何给定的周期,允许同时访问最多两个总线。

EP300 PowerPC总线仲裁器提供旋转优先级或固定的优先级方案的选择,以满足不同系统环境的要求。


  • Fully supports PowerPC™ 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260.
  • Supports up to eight PowerPC bus masters with unlimited slave device support.
  • Supports two outstanding bus accesses.
  • Supports address only transfer and address bus retry.
  • Independent address bus and data bus tenure with separate bus grant and data bus grant.
  • Option for fixed priority assignment or rotating priority scheme.
  • Designed for ASIC or programmable logic device implementations in various system environments.
  • Fully static design with edge triggered flip-flops.
  • Optimized for ispXPGA product family.

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Block Diagram



器件 利用率 性能
PFUs Slices LUTs 百分比
LFX1200B-4 17 98 41% 108Mhz
LFEC20 54 1% 133Mhz
LFXP10 54 1% 150Mhz
LFXP2-17E 54 1% 150Mhz

Ordering Information

This IP core is supported and sold by Eureka Technology, contact Eureka Technology at info@eurekatech.com or visit their website at www.eurekatech.com for more information.


标题 编号 版本 日期 格式 文件大小
PowerPC Bus Arbiter Datasheet
EP300 6/22/2007 PDF 91.9 KB