                       QDR2 Memory Controller Reference Design
=============================================================================

File list
  1. /qdr2/docs/ReadMe.txt                              --> Readme document
     /qdr2/docs/ARD.doc                                 --> Application requirment document
     /qdr2/docs/rd_1019.pdf                             --> Design document
  2. /qdr2/source/qdr2_io.v                             --> Top level file includes declarations of
                                                            HSTL1 and LVTTL I/O standards
     /qdr2/source/qdr2.v                                --> Main module of the QDR memory controller
     /qdr2/source/pipeline.v                            --> Pipeline module for increasing performance
     /qdr2/source/oddr_xp.v                             --> Output DDR module
     /qdr2/source/pll_qdr_sim.v                         --> Pll module for simulation
     /qdr2/source/pll_qdr_syn.v                         --> Pll module for synthesis
     /qdr2/source/magma.v                               --> Models for synthesis
  3. /qdr2/testbench/qdr2_tb.v     	                    --> Testbench for simulation
     /qdr2/testbench/k7r321882m_R04.v                   --> Verilog Simulation Module for Samsung K7R321882M
  4. /qdr2/synthesis/xp/synplicity/qdr2_syn.tcl         --> Script for synthesis
     /qdr2/synthesis/xp/synplicity/rev_1/qdr2_io.edn    --> Syntheis netlist
  5. /qdr2/par/xp/synplicity/qdr2.prf                   --> Over Constraint preference file
     /qdr2/par/xp/synplicity/post_route_qdr2.prf        --> Post Route Trace Constraint preference file
     /qdr2/par/xp/synplicity/qdr2_par.tcl               --> Script for running place and route
     /qdr2/par/xp/synplicity/qdr2.vo                    --> Netlist file for timing simulation
     /qdr2/par/xp/synplicity/qdr2.sdf			              --> SDF file for timing simulaiton
     /qdr2/par/xp/synplicity/qdr2_synplify_par.bat      --> Batch file for running place and route
  6. /qdr2/simulation/xp/ReadMe.txt                     --> Readme document for simulation
     /qdr2/simulation/xp/modelsim/scripts/qdr2_fsim.tcl --> Function simulation script
     /qdr2/simulation/xp/modelsim/scripts/qdr2_tsim.tcl --> Timing simulation script

Function Simulation:
  (1) Click [Tools] > [ModelSim Simulator] to launch ModelSim
  (2) Change directory to "/qdr2/simulation/xp/modelsim/rtl"
  (3) Click [Tools] > [Execute Macro] and select "../scripts/qdr2_fsim.tcl" to do function simulation

Synthesis:
  (1) Launch Synplify
  (2) Click [Run] > [Run Tcl Script]
  (3) Select "/qdr2/synthesis/xp/synplicity/qdr2_syn.tcl"

Place and Route:
  There are three way to do this:
  a) manual
  (1) Launch ispLEVER
  (2) Create a new project and name it as "qdr2" and select
      "EDIF" type and select directory "/qdr2/par/xp/synplicity"
  (3) Select device
	    Device Family: LATTICE-XP
		  Device Name  : LFXP10C
		  Speed Grade  : 4
		  Package Type : FPBGA388
  (4) Import source file "/qdr2/synthesis/xp/synplicity/rev_1/qdr2.edn"
  (5) Import constraint file from "/qdr2/par/xp/synplicity/qdr2.prf"
  (6) After creating the project right click on "Map Design" located in the right panel of the Project Navigator and select Properties.  For Pack Logic Block Util, set the value to 0.
  (7) Double click "Generate Timing Simulation Files" located in the right panel.
  (8) Import the constraint file from "/qdr2/par/xp/synplicity/post_route_qdr2.prf."
      Choose "No" when asked whether to reset the project.
  (9) Double click Place & Route TRACE Report in the right panel to view the trace report.

  b) Run tcl scripts
  (1) Launch ispLEVER Tcl Editor
  (2) Open qdr2_par.tcl, located under /qdr2/par/xp/synplicity
  (3) Modify the TCL file by setting "proj_dir" to the location of the synplicity folder for the reference design in the TCL file. For example, if the reference design is located at "d:/reference/qdr2" on your PC, you should modify the "proj_dir" to
      "d:/reference/qdr2/par/xp/synplicity" 

     You would type 

      "set proj_dir d:/reference/qdr2/par/xp/synplicity"

  
  (4) Select Run -> Start

  c) Run the batch file
  (1) Set the paths for "ISPLEVER","SYN_EDIF_DIR", and "WORK_DIR" to your own PC path in the
      file qdr2_synplify_par.bat.
  (2) Double click on the qdr2_synplify_par.bat and check the results.


Timing Simulation:
  (1) Click [Tools] > [ModelSim Simulator] to launch ModelSim
  (2) Change directory to "/qdr2/simulation/xp/modelsim/timing"
  (3) Click [Tools] > [Execute Macro] and select "../scripts/qdr2_tsim.tcl" to do timing simulation