ispLEVER 3.00.02.47.30.03_Control_Pack Fitter Report File
Copyright(C), 1992-2001, Lattice Semiconductor Corporation
All Rights Reserved
Project_Summary
Project Name : demo Project Path : C:\Shared\Demo_patterns\XPLD Project Fitted on : Fri Aug 01 14:23:37 2003 Device : SC_512_193F Package : 256 MFB Input Mux Size : 48 Available Blocks : 16 Speed : -4.5 Part Number : LC5512MV-45F256C Source Format : Schematic_Verilog_HDL Project 'demo' Fit Successfully! Compilation_Times
Prefit Time 0 secs Load Design Time 0.03 secs Partition Time 0.00 secs Place Time 0.00 secs Route Time 0.00 secs Total Fit Time 00:00:01 Design_Summary
Total Input Pins 2 Total Output Pins 10 Total Bidir Pins 0 Total Functions 10 Total Logic Functions 10 Total Arithmetic Bits 0 Total Buried Nodes 0 Total Function Nodes 0 Total Memory Nodes 0 Total Memory Blocks 0 Total Arithmetic Chains 0 Total Flip-Flops 10 Total D Flip-Flops 10 Total Latches 0 Total Product Terms 22 Total Reserved Pins 0 Total Locked Pins 12 Total Locked Nodes 0 Total Unique Output Enables 0 Total Unique Clocks 1 Total Unique Clock Enables 0 Total Unique Resets 1 Total Unique Presets 0 Device_Resource_Summary
Total Available Used Available Utilization ---------------------------------------------------------------------- Dedicated Pins Clock Pins 2 1 1 --> 50 Clock/Clock Enable Pins 2 0 2 --> 0 Enable Pins 2 0 2 --> 0 Reset Pins 1 1 0 --> 100 I/O Pins 193 10 183 --> 5 Logic Macrocells 705 10 695 --> 1 Input Registers 193 0 193 --> 0 Unusable Macrocells .. 0 .. --> .. MFB Inputs 1088 10 1078 --> 0 Logical Product Terms 2560 22 2538 --> 0 Occupied MFBs 16 1 15 --> 6 Occupied Macrocells 512 13 499 --> 2 Two Function Macrocells .. 0 .. --> .. One Function Macrocells .. 10 .. --> .. Zero Function Macrocells .. 3 .. --> .. Memory Macrocells .. 0 .. --> .. Arithmetic Macrocells .. 0 .. --> .. Occupied Product Terms 2624 43 2581 --> 1 Control Product Terms: Segment Product Term Enable 16 0 16 --> 0 MFB Clocks 16 0 16 --> 0 MFB Resets 16 0 16 --> 0 Macrocell Clocks 512 0 512 --> 0 Macrocell Clock Enables 512 0 512 --> 0 Macrocell Enables 512 0 512 --> 0 Macrocell Resets 512 0 512 --> 0 Macrocell Presets 512 0 512 --> 0 Global Routing Pool 705 10 695 --> 1 GRP from IFB .. 0 .. --> .. (from input signals) .. 0 .. --> .. (from output signals) .. 0 .. --> .. (from bidir signals) .. 0 .. --> .. GRP from MFB .. 10 .. --> .. ---------------------------------------------------------------------- <Note> 1 : A Zero Function Macrocell is a macrocell whose outputs are not used and some or all of its product terms are steered to neighboring macrocells. <Note> 2 : IFB is I/O feedback. <Note> 3 : MFB is macrocell feedback. MFB_Resource_Summary
# of PT I/O Input Macrocells Macrocells Logic clusters Fanin Pins Regs Used Unusable available PTs used ------------------------------------------------------------------------------ Maximum MFB 68 *(1) 16 -- -- 32 160 32 ============================================================================== MFB A 0 0/15 0 0 0 32 0 0 MFB B 0 0/15 0 0 0 32 0 0 MFB C 0 0/8 0 0 0 32 0 0 MFB D 0 0/14 0 0 0 32 0 0 ------------------------------------------------------------------------------ MFB E 0 0/14 0 0 0 32 0 0 MFB F 0 0/4 0 0 0 32 0 0 MFB G 0 0/10 0 0 0 32 0 0 MFB H 0 0/14 0 0 0 32 0 0 ------------------------------------------------------------------------------ MFB I 0 0/16 0 0 0 32 0 0 MFB J 0 0/8 0 0 0 32 0 0 MFB K 0 0/13 0 0 0 32 0 0 MFB L 10 10/18 0 13 0 19 22 13 ------------------------------------------------------------------------------ MFB M 0 0/18 0 0 0 32 0 0 MFB N 0 0/2 0 0 0 32 0 0 MFB O 0 0/8 0 0 0 32 0 0 MFB P 0 0/16 0 0 0 32 0 0 ------------------------------------------------------------------------------ <Note> 1 : For LC5000MX devices, the number of IOs depends on the MFB. <Note> 2 : Four rightmost columns above reflect last status of the placement process. MFB_Control_Summary
Shared Shared Segment Shared | Mcell Mcell Mcell Mcell Mcell Clock CE PT OE Reset | Clock CE Enable Reset Preset ------------------------------------------------------------------------------ Maximum MFB 1 1 1 1 32 32 32 32 32 ============================================================================== MFB A 0 0 0 0 0 0 0 0 0 MFB B 0 0 0 0 0 0 0 0 0 MFB C 0 0 0 0 0 0 0 0 0 MFB D 0 0 0 0 0 0 0 0 0 ------------------------------------------------------------------------------ MFB E 0 0 0 0 0 0 0 0 0 MFB F 0 0 0 0 0 0 0 0 0 MFB G 0 0 0 0 0 0 0 0 0 MFB H 0 0 0 0 0 0 0 0 0 ------------------------------------------------------------------------------ MFB I 0 0 0 0 0 0 0 0 0 MFB J 0 0 0 0 0 0 0 0 0 MFB K 0 0 0 0 0 0 0 0 0 MFB L 0 0 0 0 0 0 0 0 0 ------------------------------------------------------------------------------ MFB M 0 0 0 0 0 0 0 0 0 MFB N 0 0 0 0 0 0 0 0 0 MFB O 0 0 0 0 0 0 0 0 0 MFB P 0 0 0 0 0 0 0 0 0 ------------------------------------------------------------------------------ <Note> 1 : For LC5000MX devices, the number of output enables depends on the MFB. Optimizer_and_Fitter_Options
Pin Assignment : Yes Group Assignment : No Pin Reservation : No @Ignore_Project_Constraints : Pin Assignments : No Keep Block Assignment -- Keep Segment Assignment -- Group Assignments : No Macrocell Assignment : No Keep Block Assignment -- Keep Segment Assignment -- @Backannotate_Project_Constraints Pin Assignments : No Pin And Block Assignments : No Pin, Macrocell and Block : No @Timing_Constraints : No @Global_Project_Optimization : Balanced Partitioning : Yes Spread Placement : Yes Note : Pack Design : Balanced Partitioning = No Spread Placement = No Spread Design : Balanced Partitioning = Yes Spread Placement = Yes @Logic_Synthesis : Logic Reduction : Yes Node Collapsing : Speed D/T Synthesis : Yes XOR Synthesis : Yes Max. P-Term for Collapsing : 40 Max. P-Term for Splitting : 160 Max Symbols : 32 @Utilization_options Max. % of Macrocells used : 100 @Usercode (HEX) @IO_Types Default = LVCMOS25, 12 mA (2) @Output_Slew_Rate Default = FAST (2) @Power Default = HIGH (2) @Pull Default = PULLUP_UP (2) @Fast_Bypass Default = Auto (2) @Input_Registers Default = None (2) Device Options: <Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not follow the drive level set for the Global Configure Unused I/O Option. <Note> 2 : For user-specified constraints on individual signals, refer to the Output, Bidir and Buried Signal Lists. Pinout_Listing
| Pin |MFB |Assigned| | Signal| Pin No| Type |Pad |Pin | I/O Type | Type | Signal name ------------------------------------------------------------------- A1 | VCCIO0 | | | | | A2 | I_O | N5 | | | | A3 | I_O | M10| | | | A4 | I_O | M14| | | | A5 | I_O | M16| | | | A6 | I_O | M18| | | | A7 | I_O | M28| | | | A8 | I_O | L6 | * |LVCMOS25(12mA) | Output|count_5_ A9 | I_O | L12| * |LVCMOS25(12mA) | Output|count_2_ A10 | I_O | L24| | | | A11 | I_O | K0 | | | | A12 | I_O | K2 | | | | A13 | I_O | K22| | | | A14 | I_O | K24| | | | A15 | I_O | J0 | | | | A16 | VCCIO3 | | | | | B1 | I_O | O26| | | | B2 | I_O | N4 | | | | B3 | I_O | M6 | | | | B4 | I_O | M8 | | | | B5 | I_O | M12| | | | B6 | I_O | M22| | | | B7 | I_O | M30| | | | B8 | I_O | L2 | * |LVCMOS25(12mA) | Output|count_8_ B9 | I_O | L5 | * |LVCMOS25(12mA) | Output|count_6_ B10 | I_O | L26| | | | B11 | I_O | L30| | | | B12 | I_O | K18| | | | B13 | I_O | K21| | | | B14 | I_O | K28| | | | B15 | I_O | J8 | | | | B16 | I_O | J12| | | | C1 | I_O | O24| | | | C2 | I_O | O20| | | | C3 | GNDIO0 | | | | | C4 | I_O | O30| | | | C5 | I_O | M5 | | | | C6 | I_O | M4 | | | | C7 | I_O | M24| | | | C8 | I_O | L0 | * |LVCMOS25(12mA) | Output|count_9_ C9 | I_O | L20| | | | C10 | I_O | L22| | | | C11 | I_O | L28| | | | C12 | I_O | K16| | | | C13 | I_O | K26| | | | C14 | GND | | | | | C15 | I_O | J10| | | | C16 | I_O | J14| | | | D1 | I_O | P30| | | | D2 | I_O | O16| | | | D3 | I_O | O22| | | | D4 | VCC | | | | | D5 | I_O | M2 | | | | D6 | I_O | M0 | | | | D7 | I_O | M26| | | | D8 | I_O | L4 | * |LVCMOS25(12mA) | Output|count_7_ D9 | I_O | L16| | | | D10 | I_O | L21| | | | D11 | I_O | K20| | | | D12 | I_O | K30| | | | D13 | VCC | | | | | D14 | I_O | J4 | | | | D15 | I_O | I0 | | | | D16 | I_O | I2 | | | | E1 | I_O | P28| | | | E2 | I_O | P22| | | | E3 | I_O | O18| | | | E4 | I_O | O28| | | | E5 | GND | | | | | E6 | I_O | M20| | | | E7 | I_O | M21| | | | E8 | I_O | L8 | * |LVCMOS25(12mA) | Output|count_4_ E9 | I_O | L18| * |LVCMOS25(12mA) | Output|count_0_ E10 | I_O | K4 | | | | E11 | I_O | K14| | | | E12 | GND | | | | | E13 | I_O | J2 | | | | E14 | I_O | J6 | | | | E15 | I_O | I8 | | | | E16 | I_O | I16| | | | F1 | I_O | P18| | | | F2 | I_O | P20| | | | F3 | I_O | P14| | | | F4 | I_O | P26| | | | F5 | I_O | P24| | | | F6 | VCC | | | | | F7 | VCCIO0 | | | | | F8 | I_O | L10| * |LVCMOS25(12mA) | Output|count_3_ F9 | I_O | L14| * |LVCMOS25(12mA) | Output|count_1_ F10 | VCCIO3 | | | | | F11 | VCC | | | | | F12 | I_O | I6 | | | | F13 | I_O | I4 | | | | F14 | I_O | I10| | | | F15 | I_O | I24| | | | F16 | I_O | I18| | | | G1 | I_O | P16| | | | G2 | I_O | P2 | | | | G3 | I_O | P6 | | | | G4 | I_O | P8 | | | | G5 | I_O | P12| | | | G6 | VCCIO0 | | | | | G7 | GNDIO0 | | | | | G8 | GND | | | | | G9 | GNDIO3 | | | | | G10 | GND | | | | | G11 | VCCIO3 | | | | | G12 | I_O | I12| | | | G13 | I_O | I14| | | | G14 | I_O | I20| | | | G15 | I_O | I26| | | | G16 | I_O | I28| | | | H1 | I_O | P0 | | | | H2 | CLK0 | | * |LVCMOS25(12mA) | Input |clk H3 | I_O | P4 | | | | H4 | TMS | | | | | H5 | I_O | P10| | | | H6 | TDI | | | | | H7 | GND | | | | | H8 | GNDIO0 | | | | | H9 | GNDIO3 | | | | | H10 | GNDIO3 | | | | | H11 | GOE0 | | | | | H12 | I_O | I22| | | | H13 | GOE1 | | | | | H14 | I_O | I30| | | | H15 | CLK_CE2 | | | | | H16 | CLK3 | | | | | J1 | VCCJ | | | | | J2 | CLK_CE1 | | | | | J3 | I_O | A2 | | | | J4 | I_O | A6 | | | | J5 | I_O | A4 | | | | J6 | TCK | | | | | J7 | GNDIO1 | | | | | J8 | GNDIO1 | | | | | J9 | GNDIO2 | | | | | J10 | GNDIO2 | | | | | J11 | RESETB | | * |LVCMOS25(12mA) | Input |rst_n J12 | I_O | H30| | | | J13 | I_O | H26| | | | J14 | I_O | H28| | | | J15 | TOE | | | | | J16 | VCCP | | | | | K1 | GND | | | | | K2 | TDO | | | | | K3 | I_O | A0 | | | | K4 | I_O | A12| | | | K5 | I_O | A16| | | | K6 | VCCIO1 | | | | | K7 | GND | | | | | K8 | GNDIO1 | | | | | K9 | GND | | | | | K10 | GNDIO2 | | | | | K11 | VCCIO2 | | | | | K12 | I_O | H22| | | | K13 | I_O | H24| | | | K14 | I_O | H20| | | | K15 | I_O | H18| | | | K16 | GNDP | | | | | L1 | NC | | | | | L2 | I_O | A8 | | | | L3 | I_O | A14| | | | L4 | I_O | A30| | | | L5 | I_O | A18| | | | L6 | VCC | | | | | L7 | VCCIO1 | | | | | L8 | CFG0 | | | | | L9 | I_O | D10| | | | L10 | VCCIO2 | | | | | L12 | I_O | H10| | | | L11 | VCC | | | | | L13 | I_O | H8 | | | | L14 | I_O | H16| | | | L15 | I_O | H12| | | | L16 | I_O | H14| | | | M1 | I_O | A10| | | | M2 | I_O | A22| | | | M3 | I_O | A28| | | | M4 | DONE | | | | | M5 | GND | | | | | M6 | I_O | B20| | | | M7 | I_O | C12| | | | M8 | I_O | D6 | | | | M9 | I_O | D16| | | | M10 | I_O | E10| | | | M11 | I_O | E12| | | | M12 | GND | | | | | M13 | I_O | G8 | | | | M14 | I_O | H0 | | | | M15 | I_O | H2 | | | | M16 | I_O | G30| | | | N1 | I_O | A20| | | | N2 | I_O | B0 | | | | N3 | I_O | B14| | | | N4 | VCC | | | | | N5 | I_O | B18| | | | N6 | I_O | B30| | | | N7 | I_O | C28| | | | N8 | I_O | D12| | | | N9 | I_O | D28| | | | N10 | I_O | D18| | | | N11 | I_O | E26| | | | N12 | I_O | F2 | | | | N13 | VCC | | | | | N14 | I_O | G26| | | | N15 | I_O | G24| | | | N16 | I_O | G28| | | | P1 | I_O | A26| | | | P2 | I_O | B2 | | | | P3 | GND | | | | | P4 | I_O | B16| | | | P5 | I_O | B22| | | | P6 | I_O | C2 | | | | P7 | I_O | D0 | | | | P8 | I_O | D8 | | | | P9 | I_O | D26| | | | P10 | I_O | E4 | | | | P11 | I_O | E18| | | | P12 | I_O | F4 | | | | P13 | I_O | G4 | | | | P14 | I_O | G10| | | | P15 | I_O | G6 | | | | P16 | I_O | G22| | | | R1 | I_O | B4 | | | | R2 | I_O | B5 | | | | R3 | PROGRAMB | | | | | R4 | I_O | B28| | | | R5 | I_O | C0 | | | | R6 | I_O | C18| | | | R7 | I_O | C26| | | | R8 | I_O | D4 | | | | R9 | I_O | D24| | | | R10 | I_O | E6 | | | | R11 | I_O | E8 | | | | R12 | I_O | E22| | | | R13 | I_O | E24| | | | R14 | I_O | F0 | | | | R15 | I_O | F6 | | | | R16 | I_O | G20| | | | T1 | VCCIO1 | | | | | T2 | I_O | B6 | | | | T3 | I_O | B8 | | | | T4 | I_O | B24| | | | T5 | I_O | B26| | | | T6 | I_O | C16| | | | T7 | I_O | C24| | | | T8 | I_O | D2 | | | | T9 | I_O | D20| | | | T10 | I_O | D22| | | | T11 | I_O | E0 | | | | T12 | I_O | E2 | | | | T13 | I_O | E16| | | | T14 | I_O | E20| | | | T15 | I_O | E28| | | | T16 | VCCIO2 | | | | | ------------------------------------------------------------------- <Note> MFB Pad : This notation refers to the MFB I/O pad number in the device. <Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins). <Note> Pin Type : ClkIn : Dedicated input or clock pin CLK : Dedicated clock pin I_O : Input/Output pin INP : Dedicated input pin JTAG : JTAG Control and test pin NC : No connection Input_Signal_List
Input Pin Fanout Pin MFB Type Pullup Signal ------------------------------------------------ H2 -- CLK ---------------- Up clk J11 -- RST ---------------- Up rst_n ------------------------------------------------ Output_Signal_List
I C P R O Output N L Mc R E C O I F R Fanout Pin MFB P PTs S Type E S E E R P P Pwr Slew Pullup Signal ---------------------------------------------------------------------------------- E9 L 1 1 1 DFF * * 1 -----------L---- Hi Fast Up count_0_ F9 L 2 2 1 DFF * * 1 -----------L---- Hi Fast Up count_1_ A9 L 3 3 1 DFF * * 1 -----------L---- Hi Fast Up count_2_ F8 L 4 4 1 DFF * * 1 -----------L---- Hi Fast Up count_3_ E8 L 5 2 2 DFF * 1 -----------L---- Hi Fast Up count_4_ A8 L 6 2 2 DFF * 1 -----------L---- Hi Fast Up count_5_ B9 L 7 2 2 DFF * 1 -----------L---- Hi Fast Up count_6_ D8 L 8 2 2 DFF * 1 -----------L---- Hi Fast Up count_7_ B8 L 9 2 2 DFF * 1 -----------L---- Hi Fast Up count_8_ C8 L 10 2 2 DFF * 1 -----------L---- Hi Fast Up count_9_ ---------------------------------------------------------------------------------- <Note> Power : Hi = High Lo = Low <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms PRE = Has preset equation RES = Has reset equation CE = Has clock enable equation OE = Has output enable equation IR = Input register FP = Fast path used OSA = OSA path used Bidir_Signal_List
I C P R O Bidir N L Mc R E C O I F R Fanout Pin MFB P PTs S Type E S E E R P P Pwr Slew Pullup Signal -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- <Note> Power : Hi = High Lo = Low <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms PRE = Has preset equation RES = Has reset equation CE = Has clock enable equation OE = Has output enable equation IR = Input register FP = Fast path used OSA = OSA path used Buried_Signal_List
Signals_Fanout_List
Signal Source : Fanout List ------------------------------------------------------------ count_0_.Q{L}: count_0_{L} count_1_{L} count_2_{L} : count_3_{L} count_4_{L} count_5_{L} : count_6_{L} count_7_{L} count_8_{L} : count_9_{L} count_1_.Q{L}: count_1_{L} count_2_{L} count_3_{L} : count_4_{L} count_5_{L} count_6_{L} : count_7_{L} count_8_{L} count_9_{L} count_2_.Q{L}: count_2_{L} count_3_{L} count_4_{L} : count_5_{L} count_6_{L} count_7_{L} : count_8_{L} count_9_{L} count_3_.Q{L}: count_3_{L} count_4_{L} count_5_{L} : count_6_{L} count_7_{L} count_8_{L} : count_9_{L} count_4_.Q{L}: count_4_{L} count_5_{L} count_6_{L} : count_7_{L} count_8_{L} count_9_{L} count_5_.Q{L}: count_5_{L} count_6_{L} count_7_{L} : count_8_{L} count_9_{L} count_6_.Q{L}: count_6_{L} count_7_{L} count_8_{L} : count_9_{L} count_7_.Q{L}: count_7_{L} count_8_{L} count_9_{L} count_8_.Q{L}: count_8_{L} count_9_{L} count_9_.Q{L}: count_9_{L} ------------------------------------------------------------ <Note> {.} : Indicates MFB location of signal MFB_L_CLUSTER_TABLE
CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC GGGGSBBB I T L X C 0000 0000 0011 1111 1111 2222 2222 2233 CCORECCA / P P P P 0123 4567 8901 2345 6789 0123 4567 8901 KEEEBKER Type O T T T T Signal ------------------------------------------------------------------------------- M00 1--- ---- ---- ---- ---- ---- ---- -1-- 1--1---- OUT L0 0 1 1 0 count_9_ M01 -*-- ---- ---- ---- ---- ---- ---- ---- -------- M02 --1- ---- ---- ---- ---- ---- ---- ---1 1--1---- OUT L2 0 1 1 0 count_8_ M03 ---* ---- ---- ---- ---- ---- ---- ---- -------- M04 --1- 1--- ---- ---- ---- ---- ---- ---- 1--1---- OUT L4 0 1 1 0 count_7_ M05 ---1 -1-- ---- ---- ---- ---- ---- ---- 1--1---- OUT L5 0 1 1 0 count_6_ M06 ---- 1-1- ---- ---- ---- ---- ---- ---- 1--1---- OUT L6 0 1 1 0 count_5_ M07 ---- ---* ---- ---- ---- ---- ---- ---- -------- M08 ---- --1- 1--- ---- ---- ---- ---- ---- 1--1---- OUT L8 0 1 1 0 count_4_ M09 ---- ---- -*-- ---- ---- ---- ---- ---- -------- M10 ---- ---- --4- ---- ---- ---- ---- ---- 1--1---- OUT L10 0 4 0 0 count_3_ M11 ---- ---- ---* ---- ---- ---- ---- ---- -------- M12 ---- ---- ---- 3--- ---- ---- ---- ---- 1--1---- OUT L12 0 3 0 0 count_2_ M13 ---- ---- ---- -*-- ---- ---- ---- ---- -------- M14 ---- ---- ---- --2- ---- ---- ---- ---- 1--1---- OUT L14 0 2 0 0 count_1_ M15 ---- ---- ---- ---* ---- ---- ---- ---- -------- M16 ---- ---- ---- ---- *--- ---- ---- ---- -------- M17 ---- ---- ---- ---- -*-- ---- ---- ---- -------- M18 ---- ---- ---- ---- --1- ---- ---- ---- 1--1---- OUT L18 0 1 0 0 count_0_ M19 ---- ---- ---- ---- ---* ---- ---- ---- -------- M20 ---- ---- ---- ---- ---- *--- ---- ---- -------- M21 ---- ---- ---- ---- ---- -*-- ---- ---- -------- M22 ---- ---- ---- ---- ---- --*- ---- ---- -------- M23 ---- ---- ---- ---- ---- ---* ---- ---- -------- M24 ---- ---- ---- ---- ---- ---- *--- ---- -------- M25 ---- ---- ---- ---- ---- ---- -*-- ---- -------- M26 ---- ---- ---- ---- ---- ---- --*- ---- -------- M27 ---- ---- ---- ---- ---- ---- ---* ---- -------- M28 ---- ---- ---- ---- ---- ---- ---- *--- -------- M29 ---- ---- ---- ---- ---- ---- ---- -*-- -------- M30 ---- ---- ---- ---- ---- ---- ---- --*- -------- M31 ---- ---- ---- ---- ---- ---- ---- ---* -------- ------------------------------------------------------------------------------- <Note> Pin clocks, block clocks, block resets, block presets and output enables are not included in the ctrl pterm counts in the above tables. <Note> LPT = Number of Logic Pterms XPT = Number of XOR Pterms CPT = Number of Control Pterms <Note> TPT = Number of Pterm Adders <Note> GCK = Global Pin Clock GCE = Global Pin Clock Enable GOE = Global Pin Output Enable SEB = Segment Output Enable Bus GRE = Global Pin Reset BCK = Block Asynchronous Clock BCE = Block Clock Enable BAR = Block Asynchronous Reset <Note> FFP = Flag Fast Path (FIFO only) PBY = PTSA Bypass Memory Path PTE = PTSA Expander Memory Path MFB_L_LOGIC_ARRAY_FANIN
GI Source Signal GI Source Signal ----------------------------- ----------------------------- 00 mc L-0 count_9_.Q 34 ... ... 01 mc L-2 count_8_.Q 35 ... ... 02 mc L-10 count_3_.Q 36 ... ... 03 mc L-5 count_6_.Q 37 ... ... 04 ... ... 38 ... ... 05 mc L-18 count_0_.Q 39 ... ... 06 ... ... 40 ... ... 07 mc L-8 count_4_.Q 41 ... ... 08 ... ... 42 ... ... 09 mc L-4 count_7_.Q 43 ... ... 10 ... ... 44 ... ... 11 ... ... 45 ... ... 12 ... ... 46 ... ... 13 mc L-6 count_5_.Q 47 ... ... 14 ... ... 48 ... ... 15 ... ... 49 ... ... 16 ... ... 50 ... ... 17 ... ... 51 ... ... 18 ... ... 52 ... ... 19 ... ... 53 ... ... 20 mc L-14 count_1_.Q 54 ... ... 21 ... ... 55 ... ... 22 mc L-12 count_2_.Q 56 ... ... 23 ... ... 57 ... ... 24 ... ... 58 ... ... 25 ... ... 59 ... ... 26 ... ... 60 ... ... 27 ... ... 61 ... ... 28 ... ... 62 ... ... 29 ... ... 63 ... ... 30 ... ... 64 ... ... 31 ... ... 65 ... ... 32 ... ... 66 ... ... 33 ... ... 67 ... ... -------------------------------------------------------------- <Note> GI indicates the MFB inputs into the AND array. <Note> Source indicates where the signal comes from (pin or macrocell). PostFit_Equations
------------------------ Product Term Histogram ------------------------ 1 pterms : 1 ( 1) 2 pterms : 7 ( 8) 3 pterms : 1 ( 9) 4 pterms : 1 ( 10) ------------------------ <Note> The number of pterms in the above histogram counts only cluster pterms used. It does not include pterms from control equations placed on global pins or block level product terms. <Note> The value in brackets is the cumulative number of functions having less than or equal number of product terms. ------------------------ MFB Input Histogram ------------------------ 1 inputs : 1 ( 1) 2 inputs : 1 ( 2) 3 inputs : 1 ( 3) 4 inputs : 1 ( 4) 5 inputs : 1 ( 5) 6 inputs : 1 ( 6) 7 inputs : 1 ( 7) 8 inputs : 1 ( 8) 9 inputs : 1 ( 9) 10 inputs : 1 ( 10) ------------------------ <Note> The number of block inputs in the above histogram counts only signal sources that are inputs to the AND array. It does not include signal sources assigned to global pins. <Note> The value in brackets is the cumulative number of functions having less than or equal number of signal sources. count_0_.D = !count_0_.Q ; (1 pterm, 1 signal) count_0_.C = clk ; (1 pterm, 1 signal) count_0_.AR = !rst_n ; (1 pterm, 1 signal) count_1_.D = count_1_.Q & !count_0_.Q # !count_1_.Q & count_0_.Q ; (2 pterms, 2 signals) count_1_.C = clk ; (1 pterm, 1 signal) count_1_.AR = !rst_n ; (1 pterm, 1 signal) count_2_.D = !count_2_.Q & count_1_.Q & count_0_.Q # count_2_.Q & !count_1_.Q # count_2_.Q & !count_0_.Q ; (3 pterms, 3 signals) count_2_.C = clk ; (1 pterm, 1 signal) count_2_.AR = !rst_n ; (1 pterm, 1 signal) count_3_.D = !count_3_.Q & count_2_.Q & count_1_.Q & count_0_.Q # count_3_.Q & !count_1_.Q # count_3_.Q & !count_2_.Q # count_3_.Q & !count_0_.Q ; (4 pterms, 4 signals) count_3_.C = clk ; (1 pterm, 1 signal) count_3_.AR = !rst_n ; (1 pterm, 1 signal) count_4_.D.X1 = count_3_.Q & count_2_.Q & count_1_.Q & count_0_.Q ; (1 pterm, 4 signals) count_4_.D.X2 = count_4_.Q ; (1 pterm, 1 signal) count_4_.C = clk ; (1 pterm, 1 signal) count_4_.AR = !rst_n ; (1 pterm, 1 signal) count_5_.D.X1 = count_4_.Q & count_3_.Q & count_2_.Q & count_1_.Q & count_0_.Q ; (1 pterm, 5 signals) count_5_.D.X2 = count_5_.Q ; (1 pterm, 1 signal) count_5_.C = clk ; (1 pterm, 1 signal) count_5_.AR = !rst_n ; (1 pterm, 1 signal) count_6_.D.X1 = count_5_.Q & count_4_.Q & count_3_.Q & count_2_.Q & count_1_.Q & count_0_.Q ; (1 pterm, 6 signals) count_6_.D.X2 = count_6_.Q ; (1 pterm, 1 signal) count_6_.C = clk ; (1 pterm, 1 signal) count_6_.AR = !rst_n ; (1 pterm, 1 signal) count_7_.D.X1 = count_6_.Q & count_5_.Q & count_4_.Q & count_3_.Q & count_2_.Q & count_1_.Q & count_0_.Q ; (1 pterm, 7 signals) count_7_.D.X2 = count_7_.Q ; (1 pterm, 1 signal) count_7_.C = clk ; (1 pterm, 1 signal) count_7_.AR = !rst_n ; (1 pterm, 1 signal) count_8_.D.X1 = count_7_.Q & count_6_.Q & count_5_.Q & count_4_.Q & count_3_.Q & count_2_.Q & count_1_.Q & count_0_.Q ; (1 pterm, 8 signals) count_8_.D.X2 = count_8_.Q ; (1 pterm, 1 signal) count_8_.C = clk ; (1 pterm, 1 signal) count_8_.AR = !rst_n ; (1 pterm, 1 signal) count_9_.D.X1 = count_8_.Q & count_7_.Q & count_6_.Q & count_5_.Q & count_4_.Q & count_3_.Q & count_2_.Q & count_1_.Q & count_0_.Q ; (1 pterm, 9 signals) count_9_.D.X2 = count_9_.Q ; (1 pterm, 1 signal) count_9_.C = clk ; (1 pterm, 1 signal) count_9_.AR = !rst_n ; (1 pterm, 1 signal)