ispLEVER 4.1.01.29.33.04_Control_Pack_ECP_B Pack/Place Report File
Copyright(C), 1999-2003, Lattice Semiconductor Corporation
All Rights Reserved.
Project_Summary
Project Name : demo
Project Type : Schematic_Verilog_HDL
Project Synthesis Version : 2004a.53_OEM_Lattice
Synthesis Vendor : LeonardoSpectrum for Lattice
Project Path : c:\shared\demo_boards\ispxpga\lfx500c
Report Date : Tue Oct 05 10:50:07 2004
Project constraint file : demo.lct
Pack and Placement Input File : demo.ld1
Pack and Placement Output File :
Device : LFX500B
Package : 900fpBGA
Speed : -3
Part Number : LFX500B-03F900C
Project demo Packed and Placed Successfully!
User_Defined_Macros_Summary
None
Intellectual_Property_Summary
None
Error_Listing
Error count = 0
No Errors
Warning_Listing
Warning count = 0
No warnings
Note_Listing
Note count = 1
<Note> Choose Verbose to view notes.
Pack_and_Place_Options
@Ignore_Project_Constraints
Pin Assignments : NO
Group Assignments : NO
All Location Assignments : NO
Resource Reservations : NO
IO_TYPES Assignments : NO
Timing Constraints : NO
All Device Constraints : NO
@Backannotate_Project_Constraints
Pin Assignments : NO
All Location Assignments : NO
IO_TYPES Assignments : NO
All Device Constraints : NO
@Global_Constraints
Packing Density : Low
Packing Effort : High
Placement Effort : Low
Spread Placement : Off
Timing Driven Placement Effort : High
Persistent : Off
@Import_Source_Constraint : NO
Design_Summary
Total Pins : 16
Input Pins : 0
Output Pins : 14
Bi-directional Pins : 0
Clock Pins : 1
Global Set/Reset Pin : 1
Differential Pair(s) : 1
Differential Pins : 2
Reserved Pins : 0
Locked Pins : 14
Total PFU Usage : 4
LUT4s(exclude Carry Chain) : 1
Carry Chain(s) : 10
Register/Latch(s) : 10
Adder/Subtracter(s) : 0
Booth Mult(s) : 0
WLG(s) : 0
Feed-Through(s) : 1
reserved PFU(s) : 0
Total PIC Usage : 7
Register/Latch(s) : 0
Feed-Through(s) : 0
Total PLL Usage : 1
Total Differential Channels : 1
Total Receive Channel(s) : 0
HSI Receive Channel(s) : 0
Total Transmit Channel(s) : 1
HSI Transmit Channel(s) : 1
Total Bi-directional Channel(s) : 0
HSI Bi-directional Channel(s) : 0
Total EBR Usage : 0
Device_Resource_Summary
---------------------------------------------------------------------------------------------
| | Total Available | Used | Available | Utilization |
---------------------------------------------------------------------------------------------
| Dedicated Pins | 9 | 2 | 7 | 22.22 |
---------------------------------------------------------------------------------------------
| Clock Pins | 8 | 1 | 7 | 12.50 |
---------------------------------------------------------------------------------------------
| Reset Pins | 1 | 1 | 0 | 100.00 |
---------------------------------------------------------------------------------------------
| I/O Pins | 336 | 12 | 324 | 3.57 |
---------------------------------------------------------------------------------------------
| Total PFU | 1764 | 4 | 1760 | 0.23 |
---------------------------------------------------------------------------------------------
| Register/Latches | 14112 | 10 | 14102 | 0.07 |
---------------------------------------------------------------------------------------------
| Carry Chains | 7056 | 10 | 7046 | 0.14 |
---------------------------------------------------------------------------------------------
| Total PIC | 168 | 7 | 161 | 4.17 |
---------------------------------------------------------------------------------------------
| PIOs | 336 | 12 | 324 | 3.57 |
---------------------------------------------------------------------------------------------
| Register/Latches in PIC | 1008 | 0 | 1008 | 0.00 |
---------------------------------------------------------------------------------------------
PLL_Summary
PLL0 : Pin/Node Value
PLL Instance Name : I1
PLL Type : STDPLL
Input Clock : [pin] R3 clk
Output Clock : [ifb] I1 pll_clk
Secondary Output Clock :
PLL Feedback Signal :
PLL Reset Signal :
PLL Lock Signal : [ifb] I1 pll_lock_dup0
Input Clock Frequency : 20.000 MHz
Output Clock Frequency : 70.000 MHz
Secondary Clock Frequency :
Multiply (N-Divider) : 7
Divide (M-Divider) : 2
Secondary Divide (K-Divider) :
Post-scalar (V-Divider) : 2
PLL Delay Factor : 0
Wake On Lock : OFF
HSI_Receive_Mode_Summary
None
HSI_Transmit_Mode_Summary
HSI0B : Pin/Node Value
HSI Instance Name: : I2
HSI Type: : TX_10B12B
Reference Clock: : [ifb] I1 pll_clk
Transmitter Data Input[0]: : [ifb] txdata_ix22 txdata_dup0(0)
Transmitter Data Input[1]: : [ifb] txdata_ix34 txdata_dup0(1)
Transmitter Data Input[2]: : [ifb] txdata_ix41 txdata_dup0(2)
Transmitter Data Input[3]: : [ifb] txdata_ix49 txdata_dup0(3)
Transmitter Data Input[4]: : [ifb] txdata_ix56 txdata_dup0(4)
Transmitter Data Input[5]: : [ifb] txdata_ix63 txdata_dup0(5)
Transmitter Data Input[6]: : [ifb] txdata_ix70 txdata_dup0(6)
Transmitter Data Input[7]: : [ifb] txdata_ix77 txdata_dup0(7)
Transmitter Data Input[8]: : [ifb] txdata_ix84 txdata_dup0(8)
Transmitter Data Input[9]: : [ifb] txdata_ix91 txdata_dup0(9)
Transmitted Clock: :
Transmitter Output: : [pin] K1 K2 sout
CSPLL Lock Signal: : [ifb] I2 cs_lock_dup0
CSPLL M Divider Setting: : 1
CSPLL V Divider Setting: : 12
Input Clock Frequency: : 70.0000
Line Rate Frequency: : 840.00
HSI_Loop_Back_Mode_Summary
None
EBR_Summary
None
Input_Signal_List
----------------------------------------------------------------
| Signal_Name | Pin_No | Bank_IOn | IO_TYPES | PULL |
----------------------------------------------------------------
| clk | R3 | GCLK0 | LVCMOS25 | UP |
| rst_n | AK28 | RESET | LVCMOS18 | UP |
----------------------------------------------------------------
<Note> If signal names will not fit into the table, see the cross-reference below.
<Note> IO_TYPES = Assigned IO standard setting
<Note> PULL = PULL attribute setting (UP, DOWN, HOLD, OFF)
Output_Signal_List
-------------------------------------------------------------------------------------------------------------------------
| Signal_Name | Pin_No | Bank_IOn | Type | CLK | PRE | RES | CE | OE | IO_TYPES | SLEW | PULL |
-------------------------------------------------------------------------------------------------------------------------
| cs_lock | D13 | BK7_IO13 | FT | | | | | | LVCMOS25,12ma | FAST | UP |
| txdata(0) | B13 | BK7_IO14 | DFF | 0 | | rst_n | | | LVCMOS25,12ma | FAST | UP |
| txdata(1) | A13 | BK7_IO15 | DFF | 0 | | rst_n | | | LVCMOS25,12ma | FAST | UP |
| txdata(2) | F13 | BK7_IO16 | DFF | 0 | | rst_n | | | LVCMOS25,12ma | FAST | UP |
| txdata(3) | G13 | BK7_IO17 | DFF | 0 | | rst_n | | | LVCMOS25,12ma | FAST | UP |
| txdata(4) | A12 | BK7_IO18 | DFF | 0 | | rst_n | | | LVCMOS25,12ma | FAST | UP |
| txdata(5) | B12 | BK7_IO19 | DFF | 0 | | rst_n | | | LVCMOS25,12ma | FAST | UP |
| pll_lock | A7 | BK7_IO24 | FT | | | | | | LVCMOS25,12ma | FAST | UP |
| txdata(6) | B7 | BK7_IO25 | DFF | 0 | | rst_n | | | LVCMOS25,12ma | FAST | UP |
| txdata(7) | C8 | BK7_IO26 | DFF | 0 | | rst_n | | | LVCMOS25,12ma | FAST | UP |
| txdata(8) | D8 | BK7_IO27 | DFF | 0 | | rst_n | | | LVCMOS25,12ma | FAST | UP |
| txdata(9) | E8 | BK7_IO28 | DFF | 0 | | rst_n | | | LVCMOS25,12ma | FAST | UP |
| sout_n | K2 | BK0_IO11 | | | | | | | LVDS_CDR | | |
| sout_p | K1 | BK0_IO10 | | | | | | | LVDS_CDR | | |
-------------------------------------------------------------------------------------------------------------------------
<Note> If signal names will not fit into the table, see the cross-reference below.
<Note> Type = Feed-Through (FT), D-Type Registered (DFF), T-Type Registered (TFF), D-Type Latch (LAT)
<Note> CLK = The clock signal
<Note> PRE = The preset signal
<Note> RES = The reset signal
<Note> CE = The clock enable signal
<Note> OE = The output enable signal
<Note> IO_TYPES = Assigned IO standard setting
<Note> SLEW = Slew Rate setting (FAST, SLOW)
<Note> PULL = PULL attribute setting (UP, DOWN, HOLD, OFF)
Output_Signal_List_Cross_Reference
0 : pll_clk
Bi_Directional_Signal_List
<Note>There are no Bidirectional signals
Unreferenced_IO_List
<Note>There are no unreferenced IO
Compilation_Times
Load Design Time : 0.421 seconds
Pack and Place Time : 0.111 seconds
Total Pack and Placement Time : 0.546 seconds