ispLEVER 3.00.02.47.30.03_Control_Pack Pack/Place Report File
Copyright(C), 1999-2003, Lattice Semiconductor Corporation
All Rights Reserved.
Project_Summary
Project Name : demo
Project Type : Schematic_Verilog_HDL
Project Synthesis Version : 2002e.14_OEM_Lattice
Synthesis Vendor : LeonardoSpectrum for Lattice
Project Path : c:\shared\demo_patterns\xpga
Report Date : Tue Jul 29 09:44:12 2003
Project constraint file : demo.lct
Pack and Placement Input File : demo.ld1
Pack and Placement Output File :
Device : LFX1200C
Package : 900fBGA
Speed : -3
Part Number : LFX1200C-03F900C
Project demo Packed and Placed Successfully!
User_Defined_Macros_Summary
None
Intellectual_Property_Summary
None
Error_Listing
Error count = 0
No Errors
Warning_Listing
Warning count = 1
<Note> Choose Verbose to view warnings.
Note_Listing
Note count = 1
<Note> Choose Verbose to view notes.
Pack_and_Place_Options
@Ignore_Project_Constraints
Pin Assignments : NO
Group Assignments : NO
All Location Assignments : NO
Resource Reservations : NO
IO_TYPES Assignments : NO
Timing Constraints : NO
All Device Constraints : NO
@Backannotate_Project_Constraints
Pin Assignments : NO
All Location Assignments : NO
IO_TYPES Assignments : NO
All Device Constraints : NO
@Global_Constraints
Packing Density : Low
Packing Effort : High
Placement Effort : Low
Spread Placement : Off
Timing Driven Placement Effort : High
Persistent : Off
@Import_Source_Constraint : NO
Design_Summary
Total Pins : 16
Clock Pins : 1
Input Pins : 0
Output Pins : 14
Bi-directional Pins : 0
Global Set/Reset Pin : 1
Differential Pair(s) : 1
Reserved Pins : 0
Locked Pins : 14
Total PFU Usage : 4
LUT4s(exclude Carry Chain) : 1
Carry Chain(s) : 10
Register/Latch(s) : 10
Adder/Subtracter(s) : 0
Booth Mult(s) : 0
WLG(s) : 0
Feed-Through(s) : 1
reserved PFU(s) : 0
Total PIC Usage : 7
Register/Latch(s) : 0
Feed-Through(s) : 0
Total PLL Usage : 1
Total Differential Channels : 1
Total Receive Channel(s) : 0
HSI Receive Channel(s) : 0
Total Transmit Channel(s) : 1
HSI Transmit Channel(s) : 1
Total Bi-directional Channel(s) : 0
HSI Bi-directional Channel(s) : 0
Total EBR Usage : 0
Device_Resource_Summary
---------------------------------------------------------------------------------------------
| | Total Available | Used | Available | Utilization |
---------------------------------------------------------------------------------------------
| Dedicated Pins | 9 | 2 | 7 | 22.22 |
---------------------------------------------------------------------------------------------
| Clock Pins | 8 | 1 | 7 | 12.50 |
---------------------------------------------------------------------------------------------
| Reset Pins | 1 | 1 | 0 | 100.00 |
---------------------------------------------------------------------------------------------
| I/O Pins | 496 | 12 | 484 | 2.42 |
---------------------------------------------------------------------------------------------
| Total PFU | 3844 | 4 | 3840 | 0.10 |
---------------------------------------------------------------------------------------------
| Register/Latches | 30752 | 10 | 30742 | 0.03 |
---------------------------------------------------------------------------------------------
| Carry Chains | 15376 | 10 | 15366 | 0.07 |
---------------------------------------------------------------------------------------------
| Total PIC | 248 | 7 | 241 | 2.82 |
---------------------------------------------------------------------------------------------
| PIOs | 496 | 12 | 484 | 2.42 |
---------------------------------------------------------------------------------------------
| Register/Latches in PIC | 1488 | 0 | 1488 | 0.00 |
---------------------------------------------------------------------------------------------
PLL_Summary
PLL0 : Pin/Node Value
PLL Instance Name : I1
PLL Type : STDPLL
Input Clock : [pin] R3 clk
Output Clock : [ifb] I1 pll_clk
Secondary Output Clock :
PLL Feedback Signal :
PLL Reset Signal :
PLL Lock Signal : [ifb] I1 pll_lock_dup0
Input Clock Frequency : 20.000 MHz
Output Clock Frequency : 70.000 MHz
Secondary Clock Frequency :
Multiply (N-Divider) : 7
Divide (M-Divider) : 2
Secondary Divide (K-Divider) : 0
Post-scalar (V-Divider) : 2
PLL Delay Factor : 0
Wake On Lock : OFF
HSI Receive Mode Summary
None
HSI Transmit Mode Summary
HSI1A : Pin/Node Value
HSI Instance Name: : I2
HSI Type: : TX_10B12B
Reference Clock: : [ifb] I1 pll_clk
Transmitter Data Input[0]: : [ifb] txdata_ix25 txdata_dup0(0)
Transmitter Data Input[1]: : [ifb] txdata_ix35 txdata_dup0(1)
Transmitter Data Input[2]: : [ifb] txdata_ix42 txdata_dup0(2)
Transmitter Data Input[3]: : [ifb] txdata_ix49 txdata_dup0(3)
Transmitter Data Input[4]: : [ifb] txdata_ix56 txdata_dup0(4)
Transmitter Data Input[5]: : [ifb] txdata_ix63 txdata_dup0(5)
Transmitter Data Input[6]: : [ifb] txdata_ix70 txdata_dup0(6)
Transmitter Data Input[7]: : [ifb] txdata_ix77 txdata_dup0(7)
Transmitter Data Input[8]: : [ifb] txdata_ix84 txdata_dup0(8)
Transmitter Data Input[9]: : [ifb] txdata_ix91 txdata_dup0(9)
Transmitted Clock: :
Transmitter Output: : [pin] H1 H2 sout
CSPLL Lock Signal: : [ifb] I2 cs_lock_dup0
CSPLL M Divider Setting: :
CSPLL V Divider Setting: :
Input Clock Frequency: : 70.0000
Line Rate Frequency: :
HSI Loop-Back Mode Summary
None
EBR_Summary
None
Input_Signal_List
----------------------------------------------------------------
| Signal_Name | Pin_No | PIO | IO_TYPES | PULL |
----------------------------------------------------------------
| clk | R3 | GCLK0 | LVCMOS25 | UP |
| rst_n | AK28 | RESET | LVCMOS18 | UP |
----------------------------------------------------------------
<Note> If signal names will not fit into the table, see the cross-reference below.
<Note> IO_TYPES = Assigned IO standard setting
<Note> PULL = PULL attribute setting (UP, DOWN, HOLD, OFF)
Output_Signal_List
-------------------------------------------------------------------------------------------------------------------------
| Signal_Name | Pin_No | PIO | Type | CLK | PRE | RES | CE | OE | IO_TYPES | SLEW | PULL |
-------------------------------------------------------------------------------------------------------------------------
| pll_lock | AK20 | BK3_IO22 | FT | | | | | | LVCMOS25,12ma | FAST | UP |
| cs_lock | D13 | BK7_IO13 | FT | | | | | | LVCMOS25,12ma | FAST | UP |
| txdata(0) | B13 | BK7_IO14 | DFF | 0 | | rst_n | | | LVCMOS25,12ma | FAST | UP |
| txdata(1) | A13 | BK7_IO15 | DFF | 0 | | rst_n | | | LVCMOS25,12ma | FAST | UP |
| txdata(2) | F13 | BK7_IO16 | DFF | 0 | | rst_n | | | LVCMOS25,12ma | FAST | UP |
| txdata(3) | G13 | BK7_IO17 | DFF | 0 | | rst_n | | | LVCMOS25,12ma | FAST | UP |
| txdata(4) | A12 | BK7_IO18 | DFF | 0 | | rst_n | | | LVCMOS25,12ma | FAST | UP |
| txdata(5) | B12 | BK7_IO19 | DFF | 0 | | rst_n | | | LVCMOS25,12ma | FAST | UP |
| txdata(6) | C12 | BK7_IO20 | DFF | 0 | | rst_n | | | LVCMOS25,12ma | FAST | UP |
| txdata(7) | D12 | BK7_IO21 | DFF | 0 | | rst_n | | | LVCMOS25,12ma | FAST | UP |
| txdata(8) | A11 | BK7_IO22 | DFF | 0 | | rst_n | | | LVCMOS25,12ma | FAST | UP |
| txdata(9) | B11 | BK7_IO23 | DFF | 0 | | rst_n | | | LVCMOS25,12ma | FAST | UP |
| sout_n | H2 | BK0_IO23 | | | | | | | LVDS | | UP |
| sout_p | H1 | BK0_IO22 | | | | | | | LVDS | | |
-------------------------------------------------------------------------------------------------------------------------
<Note> If signal names will not fit into the table, see the cross-reference below.
<Note> Type = Feed-Through (FT), D-Type Registered (DFF), T-Type Registered (TFF), D-Type Latch (LAT)
<Note> CLK = The clock signal
<Note> PRE = The preset signal
<Note> RES = The reset signal
<Note> CE = The clock enable signal
<Note> OE = The output enable signal
<Note> IO_TYPES = Assigned IO standard setting
<Note> SLEW = Slew Rate setting (FAST, SLOW)
<Note> PULL = PULL attribute setting (UP, DOWN, HOLD, OFF)
Output_Signal_List_Cross-Reference
0 : pll_clk
Bi_Directional_Signal_List
<Note>There are no Bidirectional signals
Unreferenced_IO_List
<Note>There are no unreferenced IO
Compilation_Times
Load Design Time : 0.704 seconds
Pack and Place Time : 0.204 seconds
Total Pack and Placement Time : 0.906 seconds