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and may only be used pursuant to the terms and conditions of a written license agreement
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Tool: Synplify Pro (R)
Build: U-2023.03LR-SP1-Beta2
Install: C:\lscc\radiant\2023.2\synpbase
OS: Windows 10 or later
Hostname: L-PF4G1956

Implementation : impl_1

# Written on Wed Oct 11 10:03:01 2023

##### DESIGN INFO #######################################################

Top View:                "byteCounter"
Constraint File(s):      "C:\Users\alin\JEDI_Avant02A\LAV-AT-500X-Versa_board\TestCounter_POR-normal\byteCounter\impl_1\byteCounter_impl_1_cpe.ldc"




##### SUMMARY ############################################################

Found 0 issues in 0 out of 1 constraints


##### DETAILS ############################################################



Clock Relationships
*******************

Starting                            Ending                              |     rise to rise     |     fall to fall     |     rise to fall     |     fall to rise                     
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                              System                              |     5.000            |     No paths         |     No paths         |     No paths                         
System                              byteCounter|clk_p                   |     5.000            |     No paths         |     No paths         |     No paths                         
System                              byteCounter|jtck_inferred_clock     |     No paths         |     No paths         |     5.000            |     No paths                         
byteCounter|clk_p                   System                              |     5.000            |     No paths         |     No paths         |     No paths                         
byteCounter|clk_p                   byteCounter|clk_p                   |     5.000            |     No paths         |     No paths         |     No paths                         
byteCounter|clk_p                   byteCounter|jtck_inferred_clock     |     No paths         |     No paths         |     Diff grp         |     No paths                         
byteCounter|jtck_inferred_clock     System                              |     No paths         |     No paths         |     No paths         |     5.000                            
byteCounter|jtck_inferred_clock     byteCounter|clk_p                   |     No paths         |     No paths         |     No paths         |     Diff grp                         
byteCounter|jtck_inferred_clock     byteCounter|jtck_inferred_clock     |     No paths         |     5.000            |     No paths         |     No paths                         
===================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.


Unconstrained Start/End Points
******************************

p:TCK
p:TDI
p:TDO
p:TMS
p:led[0]
p:led[1]
p:led[2]
p:led[3]
p:led[4]
p:led[5]
p:led[6]
p:led[7]
p:rstn


Inapplicable constraints
************************

(none)


Applicable constraints with issues
**********************************

(none)


Constraints with matching wildcard expressions
**********************************************

(none)


Library Report
**************


# End of Constraint Checker Report