Lattice Timing Report - Setup and Hold, Version Radiant Software (64-bit) 2025.2.0.6.0 Wed Oct 29 13:57:41 2025 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2025 Lattice Semiconductor Corporation, All rights reserved. Command line: timing -sethld -v 10 -u 10 -endpoints 10 -nperend 1 -sp 5 -hsp m -pwrprd -html -rpt byteCounter_impl_1.twr byteCounter_impl_1.udb -gui -msgset C:/Users/clooi/Downloads/2025.2Task/DNG-26287_XO4/XO4Board/TestCounter_xo4_TestLED/byteCounter/promote.xml -------------------------------- Design: byteCounter Family: LFMXO4 Device: LFMXO4-110HC Package: BBG484 Performance: 5 Package Status: Final Version 3 **Performance Hardware Data Status : 0.0 -------------------------------- ===================================================================== Table of Contents ===================================================================== 1 Timing Overview 1.1 SDC Constraints 1.2 Constraint Coverage 1.3 Overall Summary 1.4 Unconstrained Report 1.5 Combinational Loop 2 Setup at Speed Grade 5 Corner at 85 Degrees 2.1 Clock Summary 2.2 Endpoint slacks 2.3 Detailed Report 3 Setup at Speed Grade 5 Corner at 0 Degrees 3.1 Clock Summary 3.2 Endpoint slacks 3.3 Detailed Report 4 Hold at Speed Grade m Corner at 0 Degrees 4.1 Endpoint slacks 4.2 Detailed Report ===================================================================== End of Table of Contents ===================================================================== ============================================== 1 Timing Overview ============================================== 1.1 SDC Constraints ===================== create_clock -name {clk_p} -period 18.797 [get_pins {OSCInst0/OSC }] create_clock -name {rvltck} -period 33.33 [get_ports TCK] set_false_path -to [get_clocks rvltck] set_false_path -from [get_clocks rvltck] create_generated_clock -name {rvjtck} -source [get_ports TCK] [get_nets reveal_jtck] set_false_path -to [get_clocks rvjtck] set_false_path -from [get_clocks rvjtck] 1.2 Constraint Coverage --------------------------- Constraint Coverage: 99.1897% 1.3 Overall Summary --------------------------- Setup at Speed Grade 5 Corner at 85 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns Setup at Speed Grade 5 Corner at 0 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns Hold at Speed Grade m Corner at 0 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns 1.4 Unconstrained Report =========================== 1.4.1 Unconstrained Start/End Points -------------------------------------- Clocked but unconstrained timing start points -------------------------------------------------- There is no start point satisfying reporting criteria Clocked but unconstrained timing end points ------------------------------------------------------------------- Listing 10 End Points | Type ------------------------------------------------------------------- cnt2bits_3_s_27_0/LSR | No arrival time cnt2bits_3_cry_25_0/LSR | No arrival time cnt2bits_3_cry_23_0/LSR | No arrival time cnt2bits_3_cry_21_0/LSR | No arrival time cnt2bits_3_cry_19_0/LSR | No arrival time cnt2bits_3_cry_17_0/LSR | No arrival time cnt2bits_3_cry_15_0/LSR | No arrival time cnt2bits_3_cry_13_0/LSR | No arrival time cnt2bits_3_cry_11_0/LSR | No arrival time cnt2bits_3_cry_9_0/LSR | No arrival time ------------------------------------------------------------------- | Number of unconstrained timing end poin | ts | 31 | ------------------------------------------------------------------- 1.4.2 Start/End Points Without Timing Constraints --------------------------------------------------- I/O ports without constraint ---------------------------- Possible constraints to use on I/O ports are: set_input_delay, set_output_delay, set_max_delay, create_clock, create_generated_clock, ... ------------------------------------------------------------------- Listing 9 Start or End Points | Type ------------------------------------------------------------------- rstn | input led[7] | output led[6] | output led[5] | output led[4] | output led[3] | output led[2] | output led[1] | output led[0] | output ------------------------------------------------------------------- | Number of I/O ports without constraint | 9 | ------------------------------------------------------------------- Nets without clock definition Define a clock on a top level port or a generated clock on a clock divider pin associated with this net(s). -------------------------------------------------- There is no instance satisfying reporting criteria 1.5 Combinational Loop ======================== None =============================================================== 2 Setup at Speed Grade 5 Corner at 85 Degrees =============================================================== 2.1 Clock Summary ======================= 2.1.1 Clock "clk_p" ======================= create_clock -name {clk_p} -period 18.797 [get_pins {OSCInst0/OSC }] Single Clock Domain ------------------------------------------------------------------------------------------------------- Clock clk_p | | Period | Frequency ------------------------------------------------------------------------------------------------------- From clk_p | Target | 18.797 ns | 53.200 MHz | Actual (all paths) | 10.052 ns | 99.483 MHz OSCInst0/OSC (MPW) | (50% duty cycle) | 7.500 ns | 133.333 MHz ------------------------------------------------------------------------------------------------------- Clock Domain Crossing ------------------------------------------------------------------------------------------------------ Clock clk_p | Worst Time Between Edges | Comment ------------------------------------------------------------------------------------------------------ From rvltck | ---- | False path From rvjtck | ---- | False path ------------------------------------------------------------------------------------------------------ 2.1.2 Clock "rvltck" ======================= create_clock -name {rvltck} -period 33.33 [get_ports TCK] Single Clock Domain ------------------------------------------------------------------------------------------------------- Clock rvltck | | Period | Frequency ------------------------------------------------------------------------------------------------------- From rvltck | Target | 33.330 ns | 30.003 MHz | Actual (all paths) | 6.660 ns | 150.150 MHz reveal_jtaghub_inst.IB_inst2.bb_inst/IOPAD (MPW) | (50% duty cycle) | 6.660 ns | 150.150 MHz ------------------------------------------------------------------------------------------------------- Clock Domain Crossing ------------------------------------------------------------------------------------------------------ Clock rvltck | Worst Time Between Edges | Comment ------------------------------------------------------------------------------------------------------ From clk_p | ---- | False path From rvjtck | ---- | False path ------------------------------------------------------------------------------------------------------ 2.1.3 Clock "rvjtck" ======================= create_generated_clock -name {rvjtck} -source [get_ports TCK] [get_nets reveal_jtck] Single Clock Domain ------------------------------------------------------------------------------------------------------- Clock rvjtck | | Period | Frequency ------------------------------------------------------------------------------------------------------- From rvjtck | Target | 33.330 ns | 30.003 MHz | Actual (all paths) | 6.072 ns | 164.690 MHz byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_59/CLKA (MPW) | (50% duty cycle) | 6.072 ns | 164.690 MHz ------------------------------------------------------------------------------------------------------- Clock Domain Crossing ------------------------------------------------------------------------------------------------------ Clock rvjtck | Worst Time Between Edges | Comment ------------------------------------------------------------------------------------------------------ From clk_p | ---- | False path From rvltck | ---- | False path ------------------------------------------------------------------------------------------------------ 2.2 Endpoint slacks ======================= ------------------------------------------------------- Listing 10 End Points | Slack ------------------------------------------------------- {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_28/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_26/SP} | 8.745 ns {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_23/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_21/SP} | 8.745 ns byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/tu_1/secured_instance_7_7/SP | 8.987 ns {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_48/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_45/SP} | 9.126 ns {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_40/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_37/SP} | 9.126 ns {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_31/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_29/SP} | 9.244 ns {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_44/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_41/SP} | 9.256 ns {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_35/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_34/SP} | 9.256 ns {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_20/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_17/SP} | 9.256 ns {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_58/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_57/SP} | 9.339 ns ------------------------------------------------------- | Setup # of endpoints with negative slack:| 0 | ------------------------------------------------------- 2.3 Detailed Report ======================= XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Detail report of critical paths XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q (SLICE_R16C25A) Path End : {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_28/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_26/SP} (SLICE_R24C33C) Source Clock : clk_p (R) Destination Clock: clk_p (R) Logic Level : 6 Delay Ratio : 74.6% (route), 25.4% (logic) Clock Skew : -0.096 ns Setup Constraint : 18.796 ns Common Path Skew : 0.025 ns Path Slack : 8.744 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 177 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.232 2.232 177 {byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_173/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK} CLOCK PIN 0.000 2.232 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q SLICE_R16C25A REG_DEL 0.395 2.627 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_136 NET DELAY 1.196 3.823 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/H0 SLICE_R16C28A CTOF_DEL 0.452 4.275 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_544 NET DELAY 0.518 4.793 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/H0 SLICE_R16C28C CTOF_DEL 0.360 5.153 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_signal_2_154 NET DELAY 1.612 6.765 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/H0 SLICE_R16C34D CTOF_DEL 0.452 7.217 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_signal_9_20 NET DELAY 1.293 8.510 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/A->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/H0 SLICE_R17C35C CTOF_DEL 0.360 8.870 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_31 NET DELAY 0.966 9.836 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/H0 SLICE_R19C35B CTOF_DEL 0.452 10.288 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_148 NET DELAY 1.676 11.964 8 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_28/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_26/SP} ENDPOINT 0.000 11.964 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ CONSTRAINT 0.000 18.796 1 OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 18.796 177 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.136 20.932 177 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_28/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_26/CK} CLOCK PIN 0.000 20.932 1 Uncertainty -(0.000) 20.932 Common Path Skew 0.025 20.957 Setup time -(0.249) 20.708 ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Required Time 20.708 Arrival Time -(11.963) ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Path Slack (Passed) 8.744 ++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q (SLICE_R16C25A) Path End : {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_23/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_21/SP} (SLICE_R24C33A) Source Clock : clk_p (R) Destination Clock: clk_p (R) Logic Level : 6 Delay Ratio : 74.6% (route), 25.4% (logic) Clock Skew : -0.096 ns Setup Constraint : 18.796 ns Common Path Skew : 0.025 ns Path Slack : 8.744 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 177 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.232 2.232 177 {byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_173/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK} CLOCK PIN 0.000 2.232 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q SLICE_R16C25A REG_DEL 0.395 2.627 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_136 NET DELAY 1.196 3.823 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/H0 SLICE_R16C28A CTOF_DEL 0.452 4.275 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_544 NET DELAY 0.518 4.793 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/H0 SLICE_R16C28C CTOF_DEL 0.360 5.153 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_signal_2_154 NET DELAY 1.612 6.765 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/H0 SLICE_R16C34D CTOF_DEL 0.452 7.217 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_signal_9_20 NET DELAY 1.293 8.510 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/A->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/H0 SLICE_R17C35C CTOF_DEL 0.360 8.870 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_31 NET DELAY 0.966 9.836 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/H0 SLICE_R19C35B CTOF_DEL 0.452 10.288 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_148 NET DELAY 1.676 11.964 8 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_23/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_21/SP} ENDPOINT 0.000 11.964 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ CONSTRAINT 0.000 18.796 1 OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 18.796 177 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.136 20.932 177 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_23/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_21/CK} CLOCK PIN 0.000 20.932 1 Uncertainty -(0.000) 20.932 Common Path Skew 0.025 20.957 Setup time -(0.249) 20.708 ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Required Time 20.708 Arrival Time -(11.963) ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Path Slack (Passed) 8.744 ++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q (SLICE_R16C25A) Path End : byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/tu_1/secured_instance_7_7/SP (SLICE_R14C37C) Source Clock : clk_p (R) Destination Clock: clk_p (R) Logic Level : 6 Delay Ratio : 73.0% (route), 27.0% (logic) Clock Skew : -0.096 ns Setup Constraint : 18.796 ns Common Path Skew : 0.014 ns Path Slack : 8.986 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 177 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.232 2.232 177 {byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_173/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK} CLOCK PIN 0.000 2.232 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q SLICE_R16C25A REG_DEL 0.395 2.627 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_136 NET DELAY 1.196 3.823 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/H0 SLICE_R16C28A CTOF_DEL 0.452 4.275 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_544 NET DELAY 0.518 4.793 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/H0 SLICE_R16C28C CTOF_DEL 0.452 5.245 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_signal_2_154 NET DELAY 1.636 6.881 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_3/D->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_3/H0 SLICE_R17C34C CTOF_DEL 0.452 7.333 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_signal_9_21 NET DELAY 1.047 8.380 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_1/A->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_1/H0 SLICE_R16C35B CTOF_DEL 0.360 8.740 3 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/tu_1/secured_signal_7_15 NET DELAY 1.982 10.722 3 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/tu_1/secured_instance_7_16/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/tu_1/secured_instance_7_16/H0 SLICE_R14C37D CTOF_DEL 0.452 11.174 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/tu_1/secured_signal_7_26 NET DELAY 0.537 11.711 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/tu_1/secured_instance_7_7/SP ENDPOINT 0.000 11.711 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ CONSTRAINT 0.000 18.796 1 OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 18.796 177 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.136 20.932 177 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/tu_1/secured_instance_7_7/CK CLOCK PIN 0.000 20.932 1 Uncertainty -(0.000) 20.932 Common Path Skew 0.014 20.946 Setup time -(0.249) 20.697 ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Required Time 20.697 Arrival Time -(11.710) ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Path Slack (Passed) 8.986 ++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q (SLICE_R16C25A) Path End : {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_48/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_45/SP} (SLICE_R23C34A) Source Clock : clk_p (R) Destination Clock: clk_p (R) Logic Level : 6 Delay Ratio : 73.6% (route), 26.4% (logic) Clock Skew : -0.096 ns Setup Constraint : 18.796 ns Common Path Skew : 0.025 ns Path Slack : 9.125 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 177 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.232 2.232 177 {byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_173/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK} CLOCK PIN 0.000 2.232 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q SLICE_R16C25A REG_DEL 0.395 2.627 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_136 NET DELAY 1.196 3.823 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/H0 SLICE_R16C28A CTOF_DEL 0.452 4.275 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_544 NET DELAY 0.518 4.793 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/H0 SLICE_R16C28C CTOF_DEL 0.360 5.153 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_signal_2_154 NET DELAY 1.612 6.765 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/H0 SLICE_R16C34D CTOF_DEL 0.452 7.217 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_signal_9_20 NET DELAY 1.293 8.510 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/A->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/H0 SLICE_R17C35C CTOF_DEL 0.360 8.870 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_31 NET DELAY 0.966 9.836 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/H0 SLICE_R19C35B CTOF_DEL 0.452 10.288 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_148 NET DELAY 1.295 11.583 8 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_48/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_45/SP} ENDPOINT 0.000 11.583 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ CONSTRAINT 0.000 18.796 1 OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 18.796 177 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.136 20.932 177 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_48/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_45/CK} CLOCK PIN 0.000 20.932 1 Uncertainty -(0.000) 20.932 Common Path Skew 0.025 20.957 Setup time -(0.249) 20.708 ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Required Time 20.708 Arrival Time -(11.582) ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Path Slack (Passed) 9.125 ++++ Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q (SLICE_R16C25A) Path End : {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_40/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_37/SP} (SLICE_R23C34C) Source Clock : clk_p (R) Destination Clock: clk_p (R) Logic Level : 6 Delay Ratio : 73.6% (route), 26.4% (logic) Clock Skew : -0.096 ns Setup Constraint : 18.796 ns Common Path Skew : 0.025 ns Path Slack : 9.125 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 177 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.232 2.232 177 {byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_173/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK} CLOCK PIN 0.000 2.232 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q SLICE_R16C25A REG_DEL 0.395 2.627 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_136 NET DELAY 1.196 3.823 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/H0 SLICE_R16C28A CTOF_DEL 0.452 4.275 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_544 NET DELAY 0.518 4.793 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/H0 SLICE_R16C28C CTOF_DEL 0.360 5.153 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_signal_2_154 NET DELAY 1.612 6.765 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/H0 SLICE_R16C34D CTOF_DEL 0.452 7.217 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_signal_9_20 NET DELAY 1.293 8.510 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/A->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/H0 SLICE_R17C35C CTOF_DEL 0.360 8.870 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_31 NET DELAY 0.966 9.836 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/H0 SLICE_R19C35B CTOF_DEL 0.452 10.288 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_148 NET DELAY 1.295 11.583 8 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_40/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_37/SP} ENDPOINT 0.000 11.583 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ CONSTRAINT 0.000 18.796 1 OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 18.796 177 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.136 20.932 177 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_40/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_37/CK} CLOCK PIN 0.000 20.932 1 Uncertainty -(0.000) 20.932 Common Path Skew 0.025 20.957 Setup time -(0.249) 20.708 ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Required Time 20.708 Arrival Time -(11.582) ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Path Slack (Passed) 9.125 ++++ Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q (SLICE_R16C25A) Path End : {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_31/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_29/SP} (SLICE_R21C33C) Source Clock : clk_p (R) Destination Clock: clk_p (R) Logic Level : 6 Delay Ratio : 73.3% (route), 26.7% (logic) Clock Skew : -0.060 ns Setup Constraint : 18.796 ns Common Path Skew : 0.025 ns Path Slack : 9.243 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 177 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.232 2.232 177 {byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_173/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK} CLOCK PIN 0.000 2.232 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q SLICE_R16C25A REG_DEL 0.395 2.627 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_136 NET DELAY 1.196 3.823 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/H0 SLICE_R16C28A CTOF_DEL 0.452 4.275 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_544 NET DELAY 0.518 4.793 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/H0 SLICE_R16C28C CTOF_DEL 0.360 5.153 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_signal_2_154 NET DELAY 1.612 6.765 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/H0 SLICE_R16C34D CTOF_DEL 0.452 7.217 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_signal_9_20 NET DELAY 1.293 8.510 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/A->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/H0 SLICE_R17C35C CTOF_DEL 0.360 8.870 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_31 NET DELAY 0.966 9.836 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/H0 SLICE_R19C35B CTOF_DEL 0.452 10.288 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_148 NET DELAY 1.213 11.501 8 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_31/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_29/SP} ENDPOINT 0.000 11.501 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ CONSTRAINT 0.000 18.796 1 OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 18.796 177 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.172 20.968 177 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_31/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_29/CK} CLOCK PIN 0.000 20.968 1 Uncertainty -(0.000) 20.968 Common Path Skew 0.025 20.993 Setup time -(0.249) 20.744 ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Required Time 20.744 Arrival Time -(11.500) ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Path Slack (Passed) 9.243 ++++ Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q (SLICE_R16C25A) Path End : {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_44/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_41/SP} (SLICE_R21C34A) Source Clock : clk_p (R) Destination Clock: clk_p (R) Logic Level : 6 Delay Ratio : 73.3% (route), 26.7% (logic) Clock Skew : -0.060 ns Setup Constraint : 18.796 ns Common Path Skew : 0.025 ns Path Slack : 9.255 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 177 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.232 2.232 177 {byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_173/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK} CLOCK PIN 0.000 2.232 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q SLICE_R16C25A REG_DEL 0.395 2.627 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_136 NET DELAY 1.196 3.823 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/H0 SLICE_R16C28A CTOF_DEL 0.452 4.275 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_544 NET DELAY 0.518 4.793 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/H0 SLICE_R16C28C CTOF_DEL 0.360 5.153 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_signal_2_154 NET DELAY 1.612 6.765 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/H0 SLICE_R16C34D CTOF_DEL 0.452 7.217 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_signal_9_20 NET DELAY 1.293 8.510 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/A->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/H0 SLICE_R17C35C CTOF_DEL 0.360 8.870 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_31 NET DELAY 0.966 9.836 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/H0 SLICE_R19C35B CTOF_DEL 0.452 10.288 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_148 NET DELAY 1.201 11.489 8 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_44/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_41/SP} ENDPOINT 0.000 11.489 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ CONSTRAINT 0.000 18.796 1 OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 18.796 177 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.172 20.968 177 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_44/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_41/CK} CLOCK PIN 0.000 20.968 1 Uncertainty -(0.000) 20.968 Common Path Skew 0.025 20.993 Setup time -(0.249) 20.744 ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Required Time 20.744 Arrival Time -(11.488) ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Path Slack (Passed) 9.255 ++++ Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q (SLICE_R16C25A) Path End : {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_35/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_34/SP} (SLICE_R21C34C) Source Clock : clk_p (R) Destination Clock: clk_p (R) Logic Level : 6 Delay Ratio : 73.3% (route), 26.7% (logic) Clock Skew : -0.060 ns Setup Constraint : 18.796 ns Common Path Skew : 0.025 ns Path Slack : 9.255 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 177 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.232 2.232 177 {byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_173/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK} CLOCK PIN 0.000 2.232 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q SLICE_R16C25A REG_DEL 0.395 2.627 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_136 NET DELAY 1.196 3.823 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/H0 SLICE_R16C28A CTOF_DEL 0.452 4.275 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_544 NET DELAY 0.518 4.793 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/H0 SLICE_R16C28C CTOF_DEL 0.360 5.153 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_signal_2_154 NET DELAY 1.612 6.765 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/H0 SLICE_R16C34D CTOF_DEL 0.452 7.217 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_signal_9_20 NET DELAY 1.293 8.510 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/A->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/H0 SLICE_R17C35C CTOF_DEL 0.360 8.870 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_31 NET DELAY 0.966 9.836 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/H0 SLICE_R19C35B CTOF_DEL 0.452 10.288 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_148 NET DELAY 1.201 11.489 8 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_35/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_34/SP} ENDPOINT 0.000 11.489 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ CONSTRAINT 0.000 18.796 1 OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 18.796 177 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.172 20.968 177 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_35/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_34/CK} CLOCK PIN 0.000 20.968 1 Uncertainty -(0.000) 20.968 Common Path Skew 0.025 20.993 Setup time -(0.249) 20.744 ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Required Time 20.744 Arrival Time -(11.488) ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Path Slack (Passed) 9.255 ++++ Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q (SLICE_R16C25A) Path End : {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_20/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_17/SP} (SLICE_R21C34D) Source Clock : clk_p (R) Destination Clock: clk_p (R) Logic Level : 6 Delay Ratio : 73.3% (route), 26.7% (logic) Clock Skew : -0.060 ns Setup Constraint : 18.796 ns Common Path Skew : 0.025 ns Path Slack : 9.255 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 177 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.232 2.232 177 {byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_173/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK} CLOCK PIN 0.000 2.232 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q SLICE_R16C25A REG_DEL 0.395 2.627 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_136 NET DELAY 1.196 3.823 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/H0 SLICE_R16C28A CTOF_DEL 0.452 4.275 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_544 NET DELAY 0.518 4.793 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/H0 SLICE_R16C28C CTOF_DEL 0.360 5.153 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_signal_2_154 NET DELAY 1.612 6.765 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/H0 SLICE_R16C34D CTOF_DEL 0.452 7.217 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_signal_9_20 NET DELAY 1.293 8.510 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/A->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/H0 SLICE_R17C35C CTOF_DEL 0.360 8.870 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_31 NET DELAY 0.966 9.836 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/H0 SLICE_R19C35B CTOF_DEL 0.452 10.288 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_148 NET DELAY 1.201 11.489 8 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_20/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_17/SP} ENDPOINT 0.000 11.489 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ CONSTRAINT 0.000 18.796 1 OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 18.796 177 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.172 20.968 177 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_20/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_17/CK} CLOCK PIN 0.000 20.968 1 Uncertainty -(0.000) 20.968 Common Path Skew 0.025 20.993 Setup time -(0.249) 20.744 ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Required Time 20.744 Arrival Time -(11.488) ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Path Slack (Passed) 9.255 ++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q (SLICE_R16C25A) Path End : {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_58/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_57/SP} (SLICE_R18C36D) Source Clock : clk_p (R) Destination Clock: clk_p (R) Logic Level : 6 Delay Ratio : 73.1% (route), 26.9% (logic) Clock Skew : -0.060 ns Setup Constraint : 18.796 ns Common Path Skew : 0.025 ns Path Slack : 9.338 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 177 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.232 2.232 177 {byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_173/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK} CLOCK PIN 0.000 2.232 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q SLICE_R16C25A REG_DEL 0.395 2.627 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_136 NET DELAY 1.196 3.823 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/H0 SLICE_R16C28A CTOF_DEL 0.452 4.275 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_544 NET DELAY 0.518 4.793 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/H0 SLICE_R16C28C CTOF_DEL 0.360 5.153 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_signal_2_154 NET DELAY 1.612 6.765 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/H0 SLICE_R16C34D CTOF_DEL 0.452 7.217 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_signal_9_20 NET DELAY 1.293 8.510 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/A->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/H0 SLICE_R17C35C CTOF_DEL 0.360 8.870 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_31 NET DELAY 1.192 10.062 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_90/D->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_90/H0 SLICE_R18C37B CTOF_DEL 0.452 10.514 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_146 NET DELAY 0.892 11.406 1 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_58/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_57/SP} ENDPOINT 0.000 11.406 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ CONSTRAINT 0.000 18.796 1 OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 18.796 177 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.172 20.968 177 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_58/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_57/CK} CLOCK PIN 0.000 20.968 1 Uncertainty -(0.000) 20.968 Common Path Skew 0.025 20.993 Setup time -(0.249) 20.744 ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Required Time 20.744 Arrival Time -(11.405) ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Path Slack (Passed) 9.338 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ End of Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ########################################################## =============================================================== 3 Setup at Speed Grade 5 Corner at 0 Degrees =============================================================== 3.1 Clock Summary ======================= 3.1.1 Clock "clk_p" ======================= create_clock -name {clk_p} -period 18.797 [get_pins {OSCInst0/OSC }] Single Clock Domain ------------------------------------------------------------------------------------------------------- Clock clk_p | | Period | Frequency ------------------------------------------------------------------------------------------------------- From clk_p | Target | 18.797 ns | 53.200 MHz | Actual (all paths) | 9.727 ns | 102.807 MHz OSCInst0/OSC (MPW) | (50% duty cycle) | 7.500 ns | 133.333 MHz ------------------------------------------------------------------------------------------------------- Clock Domain Crossing ------------------------------------------------------------------------------------------------------ Clock clk_p | Worst Time Between Edges | Comment ------------------------------------------------------------------------------------------------------ From rvltck | ---- | False path From rvjtck | ---- | False path ------------------------------------------------------------------------------------------------------ 3.1.2 Clock "rvltck" ======================= create_clock -name {rvltck} -period 33.33 [get_ports TCK] Single Clock Domain ------------------------------------------------------------------------------------------------------- Clock rvltck | | Period | Frequency ------------------------------------------------------------------------------------------------------- From rvltck | Target | 33.330 ns | 30.003 MHz | Actual (all paths) | 6.660 ns | 150.150 MHz reveal_jtaghub_inst.IB_inst2.bb_inst/IOPAD (MPW) | (50% duty cycle) | 6.660 ns | 150.150 MHz ------------------------------------------------------------------------------------------------------- Clock Domain Crossing ------------------------------------------------------------------------------------------------------ Clock rvltck | Worst Time Between Edges | Comment ------------------------------------------------------------------------------------------------------ From clk_p | ---- | False path From rvjtck | ---- | False path ------------------------------------------------------------------------------------------------------ 3.1.3 Clock "rvjtck" ======================= create_generated_clock -name {rvjtck} -source [get_ports TCK] [get_nets reveal_jtck] Single Clock Domain ------------------------------------------------------------------------------------------------------- Clock rvjtck | | Period | Frequency ------------------------------------------------------------------------------------------------------- From rvjtck | Target | 33.330 ns | 30.003 MHz | Actual (all paths) | 6.072 ns | 164.690 MHz byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_59/CLKA (MPW) | (50% duty cycle) | 6.072 ns | 164.690 MHz ------------------------------------------------------------------------------------------------------- Clock Domain Crossing ------------------------------------------------------------------------------------------------------ Clock rvjtck | Worst Time Between Edges | Comment ------------------------------------------------------------------------------------------------------ From clk_p | ---- | False path From rvltck | ---- | False path ------------------------------------------------------------------------------------------------------ 3.2 Endpoint slacks ======================= ------------------------------------------------------- Listing 10 End Points | Slack ------------------------------------------------------- {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_28/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_26/SP} | 9.070 ns {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_23/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_21/SP} | 9.070 ns byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/tu_1/secured_instance_7_7/SP | 9.303 ns {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_48/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_45/SP} | 9.438 ns {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_40/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_37/SP} | 9.438 ns {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_31/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_29/SP} | 9.552 ns {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_44/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_41/SP} | 9.563 ns {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_35/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_34/SP} | 9.563 ns {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_20/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_17/SP} | 9.563 ns {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_58/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_57/SP} | 9.644 ns ------------------------------------------------------- | Setup # of endpoints with negative slack:| 0 | ------------------------------------------------------- 3.3 Detailed Report ======================= XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Detail report of critical paths XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q (SLICE_R16C25A) Path End : {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_28/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_26/SP} (SLICE_R24C33C) Source Clock : clk_p (R) Destination Clock: clk_p (R) Logic Level : 6 Delay Ratio : 74.6% (route), 25.4% (logic) Clock Skew : -0.093 ns Setup Constraint : 18.796 ns Common Path Skew : 0.024 ns Path Slack : 9.069 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 178 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.161 2.161 178 {byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_173/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK} CLOCK PIN 0.000 2.161 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q SLICE_R16C25A REG_DEL 0.382 2.543 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_136 NET DELAY 1.158 3.701 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/H0 SLICE_R16C28A CTOF_DEL 0.437 4.138 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_544 NET DELAY 0.501 4.639 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/H0 SLICE_R16C28C CTOF_DEL 0.348 4.987 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_signal_2_154 NET DELAY 1.560 6.547 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/H0 SLICE_R16C34D CTOF_DEL 0.437 6.984 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_signal_9_20 NET DELAY 1.252 8.236 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/A->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/H0 SLICE_R17C35C CTOF_DEL 0.348 8.584 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_31 NET DELAY 0.935 9.519 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/H0 SLICE_R19C35B CTOF_DEL 0.437 9.956 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_148 NET DELAY 1.622 11.578 8 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_28/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_26/SP} ENDPOINT 0.000 11.578 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ CONSTRAINT 0.000 18.796 1 OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 18.796 178 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.068 20.864 178 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_28/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_26/CK} CLOCK PIN 0.000 20.864 1 Uncertainty -(0.000) 20.864 Common Path Skew 0.024 20.888 Setup time -(0.241) 20.647 ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Required Time 20.647 Arrival Time -(11.577) ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Path Slack (Passed) 9.069 ++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q (SLICE_R16C25A) Path End : {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_23/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_21/SP} (SLICE_R24C33A) Source Clock : clk_p (R) Destination Clock: clk_p (R) Logic Level : 6 Delay Ratio : 74.6% (route), 25.4% (logic) Clock Skew : -0.093 ns Setup Constraint : 18.796 ns Common Path Skew : 0.024 ns Path Slack : 9.069 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 178 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.161 2.161 178 {byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_173/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK} CLOCK PIN 0.000 2.161 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q SLICE_R16C25A REG_DEL 0.382 2.543 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_136 NET DELAY 1.158 3.701 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/H0 SLICE_R16C28A CTOF_DEL 0.437 4.138 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_544 NET DELAY 0.501 4.639 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/H0 SLICE_R16C28C CTOF_DEL 0.348 4.987 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_signal_2_154 NET DELAY 1.560 6.547 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/H0 SLICE_R16C34D CTOF_DEL 0.437 6.984 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_signal_9_20 NET DELAY 1.252 8.236 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/A->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/H0 SLICE_R17C35C CTOF_DEL 0.348 8.584 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_31 NET DELAY 0.935 9.519 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/H0 SLICE_R19C35B CTOF_DEL 0.437 9.956 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_148 NET DELAY 1.622 11.578 8 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_23/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_21/SP} ENDPOINT 0.000 11.578 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ CONSTRAINT 0.000 18.796 1 OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 18.796 178 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.068 20.864 178 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_23/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_21/CK} CLOCK PIN 0.000 20.864 1 Uncertainty -(0.000) 20.864 Common Path Skew 0.024 20.888 Setup time -(0.241) 20.647 ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Required Time 20.647 Arrival Time -(11.577) ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Path Slack (Passed) 9.069 ++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q (SLICE_R16C25A) Path End : byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/tu_1/secured_instance_7_7/SP (SLICE_R14C37C) Source Clock : clk_p (R) Destination Clock: clk_p (R) Logic Level : 6 Delay Ratio : 73.0% (route), 27.0% (logic) Clock Skew : -0.093 ns Setup Constraint : 18.796 ns Common Path Skew : 0.013 ns Path Slack : 9.302 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 178 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.161 2.161 178 {byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_173/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK} CLOCK PIN 0.000 2.161 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q SLICE_R16C25A REG_DEL 0.382 2.543 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_136 NET DELAY 1.158 3.701 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/H0 SLICE_R16C28A CTOF_DEL 0.437 4.138 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_544 NET DELAY 0.501 4.639 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/H0 SLICE_R16C28C CTOF_DEL 0.437 5.076 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_signal_2_154 NET DELAY 1.584 6.660 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_3/D->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_3/H0 SLICE_R17C34C CTOF_DEL 0.437 7.097 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_signal_9_21 NET DELAY 1.013 8.110 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_1/A->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_1/H0 SLICE_R16C35B CTOF_DEL 0.348 8.458 3 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/tu_1/secured_signal_7_15 NET DELAY 1.919 10.377 3 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/tu_1/secured_instance_7_16/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/tu_1/secured_instance_7_16/H0 SLICE_R14C37D CTOF_DEL 0.437 10.814 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/tu_1/secured_signal_7_26 NET DELAY 0.520 11.334 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/tu_1/secured_instance_7_7/SP ENDPOINT 0.000 11.334 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ CONSTRAINT 0.000 18.796 1 OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 18.796 178 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.068 20.864 178 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/tu_1/secured_instance_7_7/CK CLOCK PIN 0.000 20.864 1 Uncertainty -(0.000) 20.864 Common Path Skew 0.013 20.877 Setup time -(0.241) 20.636 ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Required Time 20.636 Arrival Time -(11.333) ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Path Slack (Passed) 9.302 ++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q (SLICE_R16C25A) Path End : {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_48/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_45/SP} (SLICE_R23C34A) Source Clock : clk_p (R) Destination Clock: clk_p (R) Logic Level : 6 Delay Ratio : 73.6% (route), 26.4% (logic) Clock Skew : -0.093 ns Setup Constraint : 18.796 ns Common Path Skew : 0.024 ns Path Slack : 9.437 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 178 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.161 2.161 178 {byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_173/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK} CLOCK PIN 0.000 2.161 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q SLICE_R16C25A REG_DEL 0.382 2.543 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_136 NET DELAY 1.158 3.701 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/H0 SLICE_R16C28A CTOF_DEL 0.437 4.138 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_544 NET DELAY 0.501 4.639 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/H0 SLICE_R16C28C CTOF_DEL 0.348 4.987 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_signal_2_154 NET DELAY 1.560 6.547 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/H0 SLICE_R16C34D CTOF_DEL 0.437 6.984 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_signal_9_20 NET DELAY 1.252 8.236 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/A->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/H0 SLICE_R17C35C CTOF_DEL 0.348 8.584 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_31 NET DELAY 0.935 9.519 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/H0 SLICE_R19C35B CTOF_DEL 0.437 9.956 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_148 NET DELAY 1.254 11.210 8 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_48/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_45/SP} ENDPOINT 0.000 11.210 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ CONSTRAINT 0.000 18.796 1 OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 18.796 178 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.068 20.864 178 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_48/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_45/CK} CLOCK PIN 0.000 20.864 1 Uncertainty -(0.000) 20.864 Common Path Skew 0.024 20.888 Setup time -(0.241) 20.647 ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Required Time 20.647 Arrival Time -(11.209) ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Path Slack (Passed) 9.437 ++++ Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q (SLICE_R16C25A) Path End : {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_40/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_37/SP} (SLICE_R23C34C) Source Clock : clk_p (R) Destination Clock: clk_p (R) Logic Level : 6 Delay Ratio : 73.6% (route), 26.4% (logic) Clock Skew : -0.093 ns Setup Constraint : 18.796 ns Common Path Skew : 0.024 ns Path Slack : 9.437 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 178 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.161 2.161 178 {byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_173/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK} CLOCK PIN 0.000 2.161 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q SLICE_R16C25A REG_DEL 0.382 2.543 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_136 NET DELAY 1.158 3.701 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/H0 SLICE_R16C28A CTOF_DEL 0.437 4.138 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_544 NET DELAY 0.501 4.639 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/H0 SLICE_R16C28C CTOF_DEL 0.348 4.987 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_signal_2_154 NET DELAY 1.560 6.547 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/H0 SLICE_R16C34D CTOF_DEL 0.437 6.984 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_signal_9_20 NET DELAY 1.252 8.236 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/A->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/H0 SLICE_R17C35C CTOF_DEL 0.348 8.584 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_31 NET DELAY 0.935 9.519 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/H0 SLICE_R19C35B CTOF_DEL 0.437 9.956 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_148 NET DELAY 1.254 11.210 8 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_40/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_37/SP} ENDPOINT 0.000 11.210 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ CONSTRAINT 0.000 18.796 1 OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 18.796 178 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.068 20.864 178 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_40/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_37/CK} CLOCK PIN 0.000 20.864 1 Uncertainty -(0.000) 20.864 Common Path Skew 0.024 20.888 Setup time -(0.241) 20.647 ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Required Time 20.647 Arrival Time -(11.209) ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Path Slack (Passed) 9.437 ++++ Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q (SLICE_R16C25A) Path End : {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_31/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_29/SP} (SLICE_R21C33C) Source Clock : clk_p (R) Destination Clock: clk_p (R) Logic Level : 6 Delay Ratio : 73.4% (route), 26.6% (logic) Clock Skew : -0.059 ns Setup Constraint : 18.796 ns Common Path Skew : 0.024 ns Path Slack : 9.551 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 178 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.161 2.161 178 {byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_173/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK} CLOCK PIN 0.000 2.161 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q SLICE_R16C25A REG_DEL 0.382 2.543 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_136 NET DELAY 1.158 3.701 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/H0 SLICE_R16C28A CTOF_DEL 0.437 4.138 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_544 NET DELAY 0.501 4.639 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/H0 SLICE_R16C28C CTOF_DEL 0.348 4.987 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_signal_2_154 NET DELAY 1.560 6.547 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/H0 SLICE_R16C34D CTOF_DEL 0.437 6.984 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_signal_9_20 NET DELAY 1.252 8.236 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/A->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/H0 SLICE_R17C35C CTOF_DEL 0.348 8.584 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_31 NET DELAY 0.935 9.519 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/H0 SLICE_R19C35B CTOF_DEL 0.437 9.956 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_148 NET DELAY 1.174 11.130 8 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_31/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_29/SP} ENDPOINT 0.000 11.130 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ CONSTRAINT 0.000 18.796 1 OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 18.796 178 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.102 20.898 178 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_31/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_29/CK} CLOCK PIN 0.000 20.898 1 Uncertainty -(0.000) 20.898 Common Path Skew 0.024 20.922 Setup time -(0.241) 20.681 ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Required Time 20.681 Arrival Time -(11.129) ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Path Slack (Passed) 9.551 ++++ Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q (SLICE_R16C25A) Path End : {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_44/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_41/SP} (SLICE_R21C34A) Source Clock : clk_p (R) Destination Clock: clk_p (R) Logic Level : 6 Delay Ratio : 73.3% (route), 26.7% (logic) Clock Skew : -0.059 ns Setup Constraint : 18.796 ns Common Path Skew : 0.024 ns Path Slack : 9.562 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 178 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.161 2.161 178 {byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_173/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK} CLOCK PIN 0.000 2.161 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q SLICE_R16C25A REG_DEL 0.382 2.543 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_136 NET DELAY 1.158 3.701 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/H0 SLICE_R16C28A CTOF_DEL 0.437 4.138 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_544 NET DELAY 0.501 4.639 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/H0 SLICE_R16C28C CTOF_DEL 0.348 4.987 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_signal_2_154 NET DELAY 1.560 6.547 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/H0 SLICE_R16C34D CTOF_DEL 0.437 6.984 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_signal_9_20 NET DELAY 1.252 8.236 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/A->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/H0 SLICE_R17C35C CTOF_DEL 0.348 8.584 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_31 NET DELAY 0.935 9.519 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/H0 SLICE_R19C35B CTOF_DEL 0.437 9.956 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_148 NET DELAY 1.163 11.119 8 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_44/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_41/SP} ENDPOINT 0.000 11.119 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ CONSTRAINT 0.000 18.796 1 OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 18.796 178 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.102 20.898 178 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_44/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_41/CK} CLOCK PIN 0.000 20.898 1 Uncertainty -(0.000) 20.898 Common Path Skew 0.024 20.922 Setup time -(0.241) 20.681 ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Required Time 20.681 Arrival Time -(11.118) ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Path Slack (Passed) 9.562 ++++ Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q (SLICE_R16C25A) Path End : {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_35/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_34/SP} (SLICE_R21C34C) Source Clock : clk_p (R) Destination Clock: clk_p (R) Logic Level : 6 Delay Ratio : 73.3% (route), 26.7% (logic) Clock Skew : -0.059 ns Setup Constraint : 18.796 ns Common Path Skew : 0.024 ns Path Slack : 9.562 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 178 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.161 2.161 178 {byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_173/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK} CLOCK PIN 0.000 2.161 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q SLICE_R16C25A REG_DEL 0.382 2.543 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_136 NET DELAY 1.158 3.701 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/H0 SLICE_R16C28A CTOF_DEL 0.437 4.138 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_544 NET DELAY 0.501 4.639 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/H0 SLICE_R16C28C CTOF_DEL 0.348 4.987 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_signal_2_154 NET DELAY 1.560 6.547 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/H0 SLICE_R16C34D CTOF_DEL 0.437 6.984 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_signal_9_20 NET DELAY 1.252 8.236 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/A->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/H0 SLICE_R17C35C CTOF_DEL 0.348 8.584 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_31 NET DELAY 0.935 9.519 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/H0 SLICE_R19C35B CTOF_DEL 0.437 9.956 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_148 NET DELAY 1.163 11.119 8 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_35/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_34/SP} ENDPOINT 0.000 11.119 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ CONSTRAINT 0.000 18.796 1 OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 18.796 178 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.102 20.898 178 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_35/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_34/CK} CLOCK PIN 0.000 20.898 1 Uncertainty -(0.000) 20.898 Common Path Skew 0.024 20.922 Setup time -(0.241) 20.681 ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Required Time 20.681 Arrival Time -(11.118) ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Path Slack (Passed) 9.562 ++++ Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q (SLICE_R16C25A) Path End : {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_20/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_17/SP} (SLICE_R21C34D) Source Clock : clk_p (R) Destination Clock: clk_p (R) Logic Level : 6 Delay Ratio : 73.3% (route), 26.7% (logic) Clock Skew : -0.059 ns Setup Constraint : 18.796 ns Common Path Skew : 0.024 ns Path Slack : 9.562 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 178 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.161 2.161 178 {byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_173/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK} CLOCK PIN 0.000 2.161 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q SLICE_R16C25A REG_DEL 0.382 2.543 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_136 NET DELAY 1.158 3.701 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/H0 SLICE_R16C28A CTOF_DEL 0.437 4.138 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_544 NET DELAY 0.501 4.639 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/H0 SLICE_R16C28C CTOF_DEL 0.348 4.987 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_signal_2_154 NET DELAY 1.560 6.547 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/H0 SLICE_R16C34D CTOF_DEL 0.437 6.984 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_signal_9_20 NET DELAY 1.252 8.236 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/A->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/H0 SLICE_R17C35C CTOF_DEL 0.348 8.584 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_31 NET DELAY 0.935 9.519 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_89/H0 SLICE_R19C35B CTOF_DEL 0.437 9.956 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_148 NET DELAY 1.163 11.119 8 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_20/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_17/SP} ENDPOINT 0.000 11.119 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ CONSTRAINT 0.000 18.796 1 OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 18.796 178 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.102 20.898 178 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_20/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_17/CK} CLOCK PIN 0.000 20.898 1 Uncertainty -(0.000) 20.898 Common Path Skew 0.024 20.922 Setup time -(0.241) 20.681 ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Required Time 20.681 Arrival Time -(11.118) ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Path Slack (Passed) 9.562 ++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q (SLICE_R16C25A) Path End : {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_58/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_57/SP} (SLICE_R18C36D) Source Clock : clk_p (R) Destination Clock: clk_p (R) Logic Level : 6 Delay Ratio : 73.1% (route), 26.9% (logic) Clock Skew : -0.059 ns Setup Constraint : 18.796 ns Common Path Skew : 0.024 ns Path Slack : 9.643 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 178 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.161 2.161 178 {byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_173/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK} CLOCK PIN 0.000 2.161 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/CK->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_172/Q SLICE_R16C25A REG_DEL 0.382 2.543 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_136 NET DELAY 1.158 3.701 5 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_407/H0 SLICE_R16C28A CTOF_DEL 0.437 4.138 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_signal_3_544 NET DELAY 0.501 4.639 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/C->byteCounter_reveal_coretop_instance/core_la0_inst_0/jtag_int_u/secured_instance_3_396/H0 SLICE_R16C28C CTOF_DEL 0.348 4.987 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_signal_2_154 NET DELAY 1.560 6.547 8 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/B->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_9/H0 SLICE_R16C34D CTOF_DEL 0.437 6.984 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_signal_9_20 NET DELAY 1.252 8.236 2 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/A->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/decode_u/secured_instance_9_0/H0 SLICE_R17C35C CTOF_DEL 0.348 8.584 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_31 NET DELAY 1.154 9.738 4 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_90/D->byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_90/H0 SLICE_R18C37B CTOF_DEL 0.437 10.175 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_signal_6_146 NET DELAY 0.863 11.038 1 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_58/SP byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_57/SP} ENDPOINT 0.000 11.038 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ CONSTRAINT 0.000 18.796 1 OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 18.796 178 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 2.102 20.898 178 {byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_58/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/trig_u/te_0/secured_instance_6_57/CK} CLOCK PIN 0.000 20.898 1 Uncertainty -(0.000) 20.898 Common Path Skew 0.024 20.922 Setup time -(0.241) 20.681 ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Required Time 20.681 Arrival Time -(11.037) ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Path Slack (Passed) 9.643 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ End of Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ########################################################## =============================================================== 4 Hold at Speed Grade m Corner at 0 Degrees =============================================================== 4.1 Endpoint slacks ======================= ------------------------------------------------------- Listing 10 End Points | Slack ------------------------------------------------------- byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_63/DIB4 | 0.167 ns byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_63/DIB3 | 0.167 ns byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_59/DIB5 | 0.167 ns byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_59/DIB4 | 0.167 ns byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_65/DIB3 | 0.184 ns byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_59/DIB6 | 0.200 ns byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_63/DIB8 | 0.251 ns byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_63/DIB6 | 0.251 ns byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_59/DIB2 | 0.251 ns byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_59/DIB1 | 0.251 ns ------------------------------------------------------- | Hold # of endpoints with negative slack: | 0 | ------------------------------------------------------- 4.2 Detailed Report ======================= XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Detail report of critical paths XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_120/Q (SLICE_R7C21B) Path End : byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_63/DIB4 (EBR_EBR_R8C19) Source Clock : clk_p (R) Destination Clock: clk_p (R) Logic Level : 1 Delay Ratio : 57.4% (route), 42.6% (logic) Clock Skew : 0.088 ns Hold Constraint : 0.000 ns Common Path Skew : -0.017 ns Path Slack : 0.167 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ------ --------------------- ------ OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 179 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 0.922 0.922 179 {byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_121/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_120/CK} CLOCK PIN 0.000 0.922 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ------ --------------------- ------ byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_120/CK->byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_120/Q SLICE_R7C21B REG_DEL 0.133 1.055 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_18 NET DELAY 0.179 1.234 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_63/DIB4 ENDPOINT 0.000 1.234 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ------ --------------------- ------ CONSTRAINT 0.000 0.000 1 OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 179 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 1.010 1.010 179 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_63/CLKB CLOCK PIN 0.000 1.010 1 Uncertainty 0.000 1.010 Common Path Skew -0.017 0.993 Hold time 0.074 1.067 ---------------------------------------- -------------- ---------------- ------ --------------------- ------ Required Time -1.067 Arrival Time 1.234 ---------------------------------------- -------------- ---------------- ------ --------------------- ------ Path Slack (Passed) 0.167 ++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_119/Q (SLICE_R7C21C) Path End : byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_63/DIB3 (EBR_EBR_R8C19) Source Clock : clk_p (R) Destination Clock: clk_p (R) Logic Level : 1 Delay Ratio : 57.4% (route), 42.6% (logic) Clock Skew : 0.088 ns Hold Constraint : 0.000 ns Common Path Skew : -0.017 ns Path Slack : 0.167 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ------ --------------------- ------ OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 179 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 0.922 0.922 179 {byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_119/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_118/CK} CLOCK PIN 0.000 0.922 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ------ --------------------- ------ byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_119/CK->byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_119/Q SLICE_R7C21C REG_DEL 0.133 1.055 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_19 NET DELAY 0.179 1.234 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_63/DIB3 ENDPOINT 0.000 1.234 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ------ --------------------- ------ CONSTRAINT 0.000 0.000 1 OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 179 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 1.010 1.010 179 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_63/CLKB CLOCK PIN 0.000 1.010 1 Uncertainty 0.000 1.010 Common Path Skew -0.017 0.993 Hold time 0.074 1.067 ---------------------------------------- -------------- ---------------- ------ --------------------- ------ Required Time -1.067 Arrival Time 1.234 ---------------------------------------- -------------- ---------------- ------ --------------------- ------ Path Slack (Passed) 0.167 ++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_85/Q (SLICE_R14C21B) Path End : byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_59/DIB5 (EBR_EBR_R15C19) Source Clock : clk_p (R) Destination Clock: clk_p (R) Logic Level : 1 Delay Ratio : 57.4% (route), 42.6% (logic) Clock Skew : 0.088 ns Hold Constraint : 0.000 ns Common Path Skew : -0.017 ns Path Slack : 0.167 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ------ --------------------- ------ OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 179 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 0.902 0.902 179 {byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_85/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_84/CK} CLOCK PIN 0.000 0.902 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ------ --------------------- ------ byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_85/CK->byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_85/Q SLICE_R14C21B REG_DEL 0.133 1.035 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_53 NET DELAY 0.179 1.214 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_59/DIB5 ENDPOINT 0.000 1.214 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ------ --------------------- ------ CONSTRAINT 0.000 0.000 1 OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 179 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 0.990 0.990 179 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_59/CLKB CLOCK PIN 0.000 0.990 1 Uncertainty 0.000 0.990 Common Path Skew -0.017 0.973 Hold time 0.074 1.047 ---------------------------------------- -------------- ---------------- ------ --------------------- ------ Required Time -1.047 Arrival Time 1.214 ---------------------------------------- -------------- ---------------- ------ --------------------- ------ Path Slack (Passed) 0.167 ++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_84/Q (SLICE_R14C21B) Path End : byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_59/DIB4 (EBR_EBR_R15C19) Source Clock : clk_p (R) Destination Clock: clk_p (R) Logic Level : 1 Delay Ratio : 57.4% (route), 42.6% (logic) Clock Skew : 0.088 ns Hold Constraint : 0.000 ns Common Path Skew : -0.017 ns Path Slack : 0.167 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ------ --------------------- ------ OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 179 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 0.902 0.902 179 {byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_85/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_84/CK} CLOCK PIN 0.000 0.902 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ------ --------------------- ------ byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_84/CK->byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_84/Q SLICE_R14C21B REG_DEL 0.133 1.035 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_54 NET DELAY 0.179 1.214 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_59/DIB4 ENDPOINT 0.000 1.214 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ------ --------------------- ------ CONSTRAINT 0.000 0.000 1 OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 179 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 0.990 0.990 179 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_59/CLKB CLOCK PIN 0.000 0.990 1 Uncertainty 0.000 0.990 Common Path Skew -0.017 0.973 Hold time 0.074 1.047 ---------------------------------------- -------------- ---------------- ------ --------------------- ------ Required Time -1.047 Arrival Time 1.214 ---------------------------------------- -------------- ---------------- ------ --------------------- ------ Path Slack (Passed) 0.167 ++++ Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_137/Q (SLICE_R7C24B) Path End : byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_65/DIB3 (EBR_EBR_R8C22) Source Clock : clk_p (R) Destination Clock: clk_p (R) Logic Level : 1 Delay Ratio : 57.4% (route), 42.6% (logic) Clock Skew : 0.088 ns Hold Constraint : 0.000 ns Common Path Skew : -0.034 ns Path Slack : 0.184 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ------ --------------------- ------ OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 179 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 0.922 0.922 179 {byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_137/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_136/CK} CLOCK PIN 0.000 0.922 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ------ --------------------- ------ byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_137/CK->byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_137/Q SLICE_R7C24B REG_DEL 0.133 1.055 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_1 NET DELAY 0.179 1.234 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_65/DIB3 ENDPOINT 0.000 1.234 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ------ --------------------- ------ CONSTRAINT 0.000 0.000 1 OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 179 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 1.010 1.010 179 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_65/CLKB CLOCK PIN 0.000 1.010 1 Uncertainty 0.000 1.010 Common Path Skew -0.034 0.976 Hold time 0.074 1.050 ---------------------------------------- -------------- ---------------- ------ --------------------- ------ Required Time -1.050 Arrival Time 1.234 ---------------------------------------- -------------- ---------------- ------ --------------------- ------ Path Slack (Passed) 0.184 ++++ Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_86/Q (SLICE_R14C21C) Path End : byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_59/DIB6 (EBR_EBR_R15C19) Source Clock : clk_p (R) Destination Clock: clk_p (R) Logic Level : 1 Delay Ratio : 61.4% (route), 38.6% (logic) Clock Skew : 0.088 ns Hold Constraint : 0.000 ns Common Path Skew : -0.017 ns Path Slack : 0.200 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ------ --------------------- ------ OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 179 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 0.902 0.902 179 {byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_87/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_86/CK} CLOCK PIN 0.000 0.902 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ------ --------------------- ------ byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_86/CK->byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_86/Q SLICE_R14C21C REG_DEL 0.133 1.035 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_52 NET DELAY 0.212 1.247 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_59/DIB6 ENDPOINT 0.000 1.247 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ------ --------------------- ------ CONSTRAINT 0.000 0.000 1 OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 179 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 0.990 0.990 179 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_59/CLKB CLOCK PIN 0.000 0.990 1 Uncertainty 0.000 0.990 Common Path Skew -0.017 0.973 Hold time 0.074 1.047 ---------------------------------------- -------------- ---------------- ------ --------------------- ------ Required Time -1.047 Arrival Time 1.247 ---------------------------------------- -------------- ---------------- ------ --------------------- ------ Path Slack (Passed) 0.200 ++++ Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_124/Q (SLICE_R7C23B) Path End : byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_63/DIB8 (EBR_EBR_R8C19) Source Clock : clk_p (R) Destination Clock: clk_p (R) Logic Level : 1 Delay Ratio : 66.4% (route), 33.6% (logic) Clock Skew : 0.088 ns Hold Constraint : 0.000 ns Common Path Skew : -0.017 ns Path Slack : 0.251 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ------ --------------------- ------ OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 179 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 0.922 0.922 179 {byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_125/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_124/CK} CLOCK PIN 0.000 0.922 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ------ --------------------- ------ byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_124/CK->byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_124/Q SLICE_R7C23B REG_DEL 0.133 1.055 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_14 NET DELAY 0.263 1.318 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_63/DIB8 ENDPOINT 0.000 1.318 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ------ --------------------- ------ CONSTRAINT 0.000 0.000 1 OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 179 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 1.010 1.010 179 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_63/CLKB CLOCK PIN 0.000 1.010 1 Uncertainty 0.000 1.010 Common Path Skew -0.017 0.993 Hold time 0.074 1.067 ---------------------------------------- -------------- ---------------- ------ --------------------- ------ Required Time -1.067 Arrival Time 1.318 ---------------------------------------- -------------- ---------------- ------ --------------------- ------ Path Slack (Passed) 0.251 ++++ Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_122/Q (SLICE_R7C22A) Path End : byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_63/DIB6 (EBR_EBR_R8C19) Source Clock : clk_p (R) Destination Clock: clk_p (R) Logic Level : 1 Delay Ratio : 66.4% (route), 33.6% (logic) Clock Skew : 0.088 ns Hold Constraint : 0.000 ns Common Path Skew : -0.017 ns Path Slack : 0.251 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ------ --------------------- ------ OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 179 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 0.922 0.922 179 {byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_123/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_122/CK} CLOCK PIN 0.000 0.922 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ------ --------------------- ------ byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_122/CK->byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_122/Q SLICE_R7C22A REG_DEL 0.133 1.055 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_16 NET DELAY 0.263 1.318 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_63/DIB6 ENDPOINT 0.000 1.318 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ------ --------------------- ------ CONSTRAINT 0.000 0.000 1 OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 179 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 1.010 1.010 179 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_63/CLKB CLOCK PIN 0.000 1.010 1 Uncertainty 0.000 1.010 Common Path Skew -0.017 0.993 Hold time 0.074 1.067 ---------------------------------------- -------------- ---------------- ------ --------------------- ------ Required Time -1.067 Arrival Time 1.318 ---------------------------------------- -------------- ---------------- ------ --------------------- ------ Path Slack (Passed) 0.251 ++++ Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_82/Q (SLICE_R13C21B) Path End : byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_59/DIB2 (EBR_EBR_R15C19) Source Clock : clk_p (R) Destination Clock: clk_p (R) Logic Level : 1 Delay Ratio : 66.4% (route), 33.6% (logic) Clock Skew : 0.088 ns Hold Constraint : 0.000 ns Common Path Skew : -0.017 ns Path Slack : 0.251 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ------ --------------------- ------ OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 179 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 0.902 0.902 179 {byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_83/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_82/CK} CLOCK PIN 0.000 0.902 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ------ --------------------- ------ byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_82/CK->byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_82/Q SLICE_R13C21B REG_DEL 0.133 1.035 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_56 NET DELAY 0.263 1.298 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_59/DIB2 ENDPOINT 0.000 1.298 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ------ --------------------- ------ CONSTRAINT 0.000 0.000 1 OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 179 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 0.990 0.990 179 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_59/CLKB CLOCK PIN 0.000 0.990 1 Uncertainty 0.000 0.990 Common Path Skew -0.017 0.973 Hold time 0.074 1.047 ---------------------------------------- -------------- ---------------- ------ --------------------- ------ Required Time -1.047 Arrival Time 1.298 ---------------------------------------- -------------- ---------------- ------ --------------------- ------ Path Slack (Passed) 0.251 ++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_81/Q (SLICE_R13C21A) Path End : byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_59/DIB1 (EBR_EBR_R15C19) Source Clock : clk_p (R) Destination Clock: clk_p (R) Logic Level : 1 Delay Ratio : 66.4% (route), 33.6% (logic) Clock Skew : 0.088 ns Hold Constraint : 0.000 ns Common Path Skew : -0.017 ns Path Slack : 0.251 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ------ --------------------- ------ OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 179 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 0.902 0.902 179 {byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_81/CK byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_80/CK} CLOCK PIN 0.000 0.902 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ------ --------------------- ------ byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_81/CK->byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_81/Q SLICE_R13C21A REG_DEL 0.133 1.035 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_57 NET DELAY 0.263 1.298 1 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_59/DIB1 ENDPOINT 0.000 1.298 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ------ --------------------- ------ CONSTRAINT 0.000 0.000 1 OSCInst0/OSC OSC_OSC CLOCK LATENCY 0.000 0.000 179 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_signal_1_138 NET DELAY 0.990 0.990 179 byteCounter_reveal_coretop_instance/core_la0_inst_0/tm_u/secured_instance_2_379/secured_instance_1_59/CLKB CLOCK PIN 0.000 0.990 1 Uncertainty 0.000 0.990 Common Path Skew -0.017 0.973 Hold time 0.074 1.047 ---------------------------------------- -------------- ---------------- ------ --------------------- ------ Required Time -1.047 Arrival Time 1.298 ---------------------------------------- -------------- ---------------- ------ --------------------- ------ Path Slack (Passed) 0.251 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ End of Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ##########################################################