Timing Report
Lattice Timing Report - Setup and Hold, Version Radiant Software (64-bit) 2023.1.0.43.3
Thu Jul 20 12:17:24 2023
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Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.
Command line: timing -sethld -v 10 -u 10 -endpoints 10 -nperend 1 -html -rpt byteCounter_impl_1.tws byteCounter_impl_1_syn.udb -gui
-------------------------------------------
Design: byteCounter
Family: LFCPNX
Device: LFCPNX-100
Package: LFG672
Performance: 7_High-Performance_1.0V
Package Status: Final Version 16
-------------------------------------------
=====================================================================
Table of Contents
=====================================================================
1 DESIGN CHECKING
1.1 SDC Constraints
1.2 Constraint Coverage
1.3 Overall Summary
1.4 Unconstrained Report
1.5 Combinational Loop
2 Setup at Speed Grade 7_High-Performance_1.0V Corner at 100 Degrees
2.1 Clock Summary
2.2 Endpoint slacks
2.3 Detailed Report
3 Hold at Speed Grade M Corner at -40 Degrees
3.1 Endpoint slacks
3.2 Detailed Report
=====================================================================
End of Table of Contents
=====================================================================
1 DESIGN CHECKING
1.1 SDC Constraints
create_clock -name {rvltck} -period 33.33 [get_ports TCK]
set_false_path -to [get_clocks rvltck]
1.2 Constraint Coverage
Constraint Coverage: 1.07925%
1.3 Overall Summary
Setup at Speed Grade 7_High-Performance_1.0V Corner at 100 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns
Hold at Speed Grade M Corner at -40 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns
1.4 Unconstrained Report
1.4.1 Unconstrained Start/End Points
Clocked but unconstrained timing start points
--------------------------------------------------
There is no start point satisfying reporting criteria
Clocked but unconstrained timing end points
-------------------------------------------------------------------
Listing 10 End Points | Type
-------------------------------------------------------------------
reveal_coretop_i19101/bytecounter_la0_inst_0/trig_u/tu_2/wr_din_0__I_0_14.ff_inst/CE
| No arrival or required
reveal_coretop_i19101/bytecounter_la0_inst_0/trig_u/tu_2/wr_din_0__I_0_12.ff_inst/CE
| No arrival or required
reveal_coretop_i19101/bytecounter_la0_inst_0/trig_u/tu_2/wr_din_1__I_0_8.ff_inst/CE
| No arrival or required
reveal_coretop_i19101/bytecounter_la0_inst_0/trig_u/tu_2/wr_din_2__I_0_7.ff_inst/CE
| No arrival or required
reveal_coretop_i19101/bytecounter_la0_inst_0/trig_u/tu_2/c_I_0.ff_inst/DF
| No arrival or required
reveal_coretop_i19101/bytecounter_la0_inst_0/trig_u/tu_2/wr_din_0__I_0_13.ff_inst/CE
| No arrival or required
reveal_coretop_i19101/bytecounter_la0_inst_0/trig_u/tu_2/input_a_d1_0__I_0_2.ff_inst/DF
| No arrival or required
reveal_coretop_i19101/bytecounter_la0_inst_0/trig_u/tu_1/wr_din_0__I_0_11.ff_inst/CE
| No arrival or required
reveal_coretop_i19101/bytecounter_la0_inst_0/trig_u/tu_1/wr_din_0__I_0_9.ff_inst/CE
| No arrival or required
reveal_coretop_i19101/bytecounter_la0_inst_0/trig_u/tu_1/wr_din_1__I_0_7.ff_inst/CE
| No arrival or required
-------------------------------------------------------------------
|
Number of unconstrained timing end poin |
ts | 537
|
-------------------------------------------------------------------
1.4.2 Start/End Points Without Timing Constraints
I/O ports without constraint
----------------------------
Possible constraints to use on I/O ports are:
set_input_delay,
set_output_delay,
set_max_delay,
create_clock,
create_generated_clock,
...
-------------------------------------------------------------------
Listing 10 Start or End Points | Type
-------------------------------------------------------------------
rstn | input
TMS | input
TDI | input
led[7] | output
led[6] | output
led[5] | output
led[4] | output
led[3] | output
led[2] | output
led[1] | output
-------------------------------------------------------------------
|
Number of I/O ports without constraint | 11
|
-------------------------------------------------------------------
Nets without clock definition
Define a clock on a top level port or a generated clock on a clock divider pin associated with this net(s).
-------------------------------------------------------------------
Listing 1 Net(s) | Source pin
-------------------------------------------------------------------
clk_p_c | clk_p_pad.bb_inst/O
-------------------------------------------------------------------
|
Number of clock nets without clock defi |
nition | 1
|
-------------------------------------------------------------------
1.5 Combinational Loop
None
2 Setup at Speed Grade 7_High-Performance_1.0V Corner at 100 Degrees
2.1 Clock Summary
2.1.1 Clock "rvltck"
create_clock -name {rvltck} -period 33.33 [get_ports TCK]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock rvltck | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From rvltck | Target | 33.330 ns | 30.003 MHz
| Actual (all paths) | 5.000 ns | 200.000 MHz
jtaghub_inst/IB_inst2.bb_inst/B (MPW) | (50% duty cycle) | 5.000 ns | 200.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
2.2 Endpoint slacks
--------------------------------------------------
There is no end point satisfying reporting criteria
Total Negative Slack: 0
2.3 Detailed Report
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Detail report of critical paths
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+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
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+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
##########################################################
3 Hold at Speed Grade M Corner at -40 Degrees
3.1 Endpoint slacks
--------------------------------------------------
There is no end point satisfying reporting criteria
Total Negative Slack: 0
3.2 Detailed Report
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Detail report of critical paths
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
##########################################################