Synthesis and Ngdbuild Report
#Build: Synplify Pro for Lattice D-2010.03L-SP1, Build 142R, Aug 11 2010
#install: C:\ispTOOLS8_1\synpbase
#OS: Windows_NT
#Hostname: L25793
$ Start of Compile
#Mon Oct 04 16:26:25 2010
Synopsys Verilog Compiler, version comp510rc, Build 126R, built Jul 22 2010
@N|Running in 32-bit mode
Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved
@I::"C:\ispTOOLS8_1\synpbase\lib\lucent\xp2.v"
@I::"C:\ispTOOLS8_1\ispcpld\..\cae_library\synthesis\verilog\XP2.v"
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\project\control_SoC_demo.h"
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\wave_read.v"
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\clk_gen.v"
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\audio_buffer.v"
@I:"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\audio_buffer.v":".\timescale.v"
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v"
@I:"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\timescale.v"
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\rom_ebr_wb.v"
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1044\Source\Spi_wb.v"
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_registers.v"
@I:"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_registers.v":"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\..\testbench\timescale.v"
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_bit_ctrl.v"
@N: CG334 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_bit_ctrl.v":161:12:161:24|Read directive translate_off
@N: CG333 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_bit_ctrl.v":163:12:163:23|Read directive translate_on
@I:"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_bit_ctrl.v":"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_defines.v"
@N: CG346 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_bit_ctrl.v":394:38:394:46|Read full_case directive
@N: CG347 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_bit_ctrl.v":394:48:394:60|Read parallel_case directive
@N: CG346 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_bit_ctrl.v":398:40:398:48|Read full_case directive
@N: CG347 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_bit_ctrl.v":398:50:398:62|Read parallel_case directive
@W: CG286 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_bit_ctrl.v":398:17:398:20|Case statement has both a full_case directive and a default clause. The full_case directive is ignored.
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_byte_ctrl.v"
@N: CG334 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_byte_ctrl.v":106:12:106:24|Read directive translate_off
@N: CG333 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_byte_ctrl.v":108:12:108:23|Read directive translate_on
@N: CG346 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_byte_ctrl.v":275:34:275:42|Read full_case directive
@N: CG347 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_byte_ctrl.v":275:44:275:56|Read parallel_case directive
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_wb_top.v"
@N: CG334 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_wb_top.v":110:12:110:24|Read directive translate_off
@N: CG333 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_wb_top.v":112:12:112:23|Read directive translate_on
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\modem.v"
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\uart_core.v"
@I:"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\uart_core.v":"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v"
@I:"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\txcver_fifo.v"
@I:"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\txcver_fifo.v":"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\system_conf.v"
@I:"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\uart_core.v":"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v"
@I:"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver_fifo.v"
@I:"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\uart_core.v":"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\txmitt.v"
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\lm8_top.v"
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_io_cntl.v"
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_flow_cntl.v"
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_alu.v"
@N: CG347 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_alu.v":176:35:176:47|Read parallel_case directive
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_idec.v"
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1066\source\verilog\box_ave.v"
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1066\source\verilog\sigmadelta_adc.v"
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1066\source\verilog\adc_top.v"
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\adc_wb.v"
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1043\source\lm8_wb.v"
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\led_sw_wb.v"
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\reset_gen.v"
@W: CG479 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\reset_gen.v":60:4:60:11|rst1_out is already declared in this scope.
@W: CG479 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\reset_gen.v":61:4:61:11|rst2_out is already declared in this scope.
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\crc16.v"
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\fifo.v"
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v"
@W: CG479 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":71:11:71:16|fifo_d is already declared in this scope.
@W: CG479 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":72:11:72:16|fifo_q is already declared in this scope.
@W: CG479 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":78:6:78:14|fifo_rden is already declared in this scope.
@W: CG479 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":79:6:79:14|fifo_wren is already declared in this scope.
@W: CG479 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":81:6:81:13|select_0 is already declared in this scope.
@W: CG479 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":82:6:82:13|select_1 is already declared in this scope.
@W: CG479 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":84:6:84:15|fifo_empty is already declared in this scope.
@W: CG479 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":85:6:85:17|fifo_empty_p is already declared in this scope.
@W: CG479 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":87:6:87:16|fifo_f_flag is already declared in this scope.
@W: CG479 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":93:8:93:20|sd_bit_sel_tx is already declared in this scope.
@W: CG479 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":94:8:94:20|data_tristate is already declared in this scope.
@W: CG479 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":97:11:97:24|crc16_d0_shift is already declared in this scope.
@W: CG479 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":98:11:98:24|crc16_d1_shift is already declared in this scope.
@W: CG479 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":99:11:99:24|crc16_d2_shift is already declared in this scope.
@W: CG479 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":100:11:100:24|crc16_d3_shift is already declared in this scope.
@W: CG479 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":102:12:102:19|crc16_d0 is already declared in this scope.
@W: CG479 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":103:12:103:19|crc16_d1 is already declared in this scope.
@W: CG479 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":104:12:104:19|crc16_d2 is already declared in this scope.
@W: CG479 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":105:12:105:19|crc16_d3 is already declared in this scope.
@W: CG479 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":108:5:108:14|res_detect is already declared in this scope.
@W: CG479 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":109:5:109:17|res_shift_rst is already declared in this scope.
@W: CG479 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":110:5:110:13|res_shift is already declared in this scope.
@W: CG479 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":111:4:111:18|card_bit_sel_tx is already declared in this scope.
@W: CG479 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":114:10:114:19|crc16_load is already declared in this scope.
@W: CG479 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":117:7:117:19|crc16_tx_done is already declared in this scope.
@W: CG479 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":118:10:118:20|crc16_count is already declared in this scope.
@W: CG479 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":356:4:356:19|pause_crc16_load is already declared in this scope.
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\crc7.v"
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\cmd_phy.v"
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\sd_core.v"
@I::"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\xo_control_soc_demo.v"
@W: CG479 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\xo_control_soc_demo.v":159:7:159:13|sd_clk2 is already declared in this scope.
Verilog syntax check successful!
Selecting top level module xo_mini_soc_demo
@N: CG364 :"C:\ispTOOLS8_1\ispcpld\..\cae_library\synthesis\verilog\XP2.v":186:7:186:8|Synthesizing module BB
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\crc7.v":80:7:80:10|Synthesizing module CRC7
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\cmd_phy.v":2:7:2:13|Synthesizing module CMD_PHY
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\cmd_phy.v":210:8:210:10|Removing redundant assignment
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\cmd_phy.v":222:13:222:20|Removing redundant assignment
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\cmd_phy.v":249:11:249:16|Removing redundant assignment
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\cmd_phy.v":263:16:263:24|Removing redundant assignment
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\cmd_phy.v":327:14:327:22|Removing redundant assignment
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\cmd_phy.v":351:13:351:20|Removing redundant assignment
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\cmd_phy.v":352:11:352:15|Removing redundant assignment
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\cmd_phy.v":380:11:380:13|Removing redundant assignment
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\fifo.v":2:7:2:14|Synthesizing module pmi_fifo
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\crc16.v":6:7:6:11|Synthesizing module CRC16
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":3:7:3:14|Synthesizing module DATA_PHY
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":160:16:160:26|Removing redundant assignment
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":162:16:162:26|Removing redundant assignment
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":273:16:273:26|Removing redundant assignment
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":299:19:299:32|Removing redundant assignment
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":319:19:319:32|Removing redundant assignment
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":332:19:332:32|Removing redundant assignment
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":345:19:345:32|Removing redundant assignment
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":371:16:371:25|Removing redundant assignment
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":441:14:441:22|Removing redundant assignment
@W: CL118 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":140:1:140:2|Latch generated from always block for signal fifo_o[7:0], probably caused by a missing assignment in an if or case stmt
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\sd_core.v":1:7:1:13|Synthesizing module SD_CORE
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\sd_core.v":147:17:147:28|Removing redundant assignment
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\sd_core.v":148:15:148:24|Removing redundant assignment
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\sd_core.v":149:15:149:24|Removing redundant assignment
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\sd_core.v":150:15:150:24|Removing redundant assignment
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\sd_core.v":151:15:151:24|Removing redundant assignment
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\sd_core.v":152:15:152:24|Removing redundant assignment
@W: CG781 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\sd_core.v":178:12:178:21|Undriven input we_i on instance CMD_PHY_i0, tying to 0
@W: CG781 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\sd_core.v":234:15:234:15|Undriven input cmd_control_wb on instance DATA_PHY_i0, tying to 0
@W: CL170 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\sd_core.v":124:0:124:5|Pruning bit <7> of control_wb_r[7:0] - not in use ...
@W: CL170 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\sd_core.v":124:0:124:5|Pruning bit <6> of control_wb_r[7:0] - not in use ...
@W: CL170 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\sd_core.v":124:0:124:5|Pruning bit <5> of control_wb_r[7:0] - not in use ...
@W: CL170 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\sd_core.v":124:0:124:5|Pruning bit <4> of control_wb_r[7:0] - not in use ...
@W: CL170 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\sd_core.v":124:0:124:5|Pruning bit <3> of control_wb_r[7:0] - not in use ...
@W: CL170 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\sd_core.v":124:0:124:5|Pruning bit <7> of cmd_0_wb_r[7:0] - not in use ...
@W: CL170 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\sd_core.v":124:0:124:5|Pruning bit <6> of cmd_0_wb_r[7:0] - not in use ...
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\reset_gen.v":46:7:46:15|Synthesizing module reset_gen
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\led_sw_wb.v":46:7:46:15|Synthesizing module led_sw_wb
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1043\source\lm8_wb.v":46:7:46:12|Synthesizing module lm8_wb
LM8_ADDR_W=32'b00000000000000000000000000011000
NUM_DECODE=32'b00000000000000000000000000000100
WB_ADDR_W=32'b00000000000000000000000000010100
NUM_SLAVES=32'b00000000000000000000000000010000
Generated name = lm8_wb_24s_4s_20s_16s
@N: CG364 :"C:\ispTOOLS8_1\ispcpld\..\cae_library\synthesis\verilog\XP2.v":25:7:25:11|Synthesizing module ILVDS
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1066\source\verilog\box_ave.v":66:7:66:13|Synthesizing module box_ave
ADC_WIDTH=32'b00000000000000000000000000001000
LPF_DEPTH_BITS=32'b00000000000000000000000000000011
Generated name = box_ave_8s_3s
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1066\source\verilog\sigmadelta_adc.v":62:7:62:20|Synthesizing module sigmadelta_adc
ADC_WIDTH=32'b00000000000000000000000000001000
ACCUM_BITS=32'b00000000000000000000000000001010
LPF_DEPTH_BITS=32'b00000000000000000000000000000011
Generated name = sigmadelta_adc_8s_10s_3s
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1066\source\verilog\adc_top.v":62:7:62:13|Synthesizing module ADC_top
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\adc_wb.v":46:7:46:12|Synthesizing module adc_wb
@W: CG133 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\adc_wb.v":54:19:54:21|No assignment to led
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_idec.v":40:7:40:15|Synthesizing module isp8_idec
PROM_AW=32'b00000000000000000000000000001010
Generated name = isp8_idec_10s
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_alu.v":200:7:200:16|Synthesizing module pmi_addsub
pmi_data_width=32'b00000000000000000000000000001000
pmi_result_width=32'b00000000000000000000000000001000
pmi_sign=24'b011011110110011001100110
pmi_family=24'b010110000100111100110010
module_type=80'b01110000011011010110100101011111011000010110010001100100011100110111010101100010
Generated name = pmi_addsub_8s_8s_off_XO2_pmi_addsub
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_alu.v":41:7:41:14|Synthesizing module isp8_alu
FAMILY_NAME=24'b010110000100111100110010
Generated name = isp8_alu_XO2
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\lm8_top.v":142:7:142:27|Synthesizing module pmi_distributed_spram
pmi_addr_depth=32'b00000000000000000000000000010000
pmi_addr_width=32'b00000000000000000000000000000100
pmi_data_width=32'b00000000000000000000000000001100
pmi_regmode=40'b0110111001101111011100100110010101100111
pmi_init_file=32'b01101110011011110110111001100101
pmi_init_file_format=48'b011000100110100101101110011000010111001001111001
pmi_family=24'b010110000100111100110010
module_type=168'b011100000110110101101001010111110110010001101001011100110111010001110010011010010110001001110101011101000110010101100100010111110111001101110000011100100110000101101101
Generated name = pmi_distributed_spram_16s_4s_12s_noreg_none_binary_XO2_pmi_distributed_spram_Z1
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_flow_cntl.v":40:7:40:20|Synthesizing module isp8_flow_cntl
PGM_STACK_AW=32'b00000000000000000000000000000100
PGM_STACK_AD=32'b00000000000000000000000000010000
PROM_AW=32'b00000000000000000000000000001010
FAMILY_NAME=24'b010110000100111100110010
Generated name = isp8_flow_cntl_4s_16s_10s_XO2
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_flow_cntl.v":222:20:222:28|Removing redundant assignment
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_flow_cntl.v":288:30:288:43|Removing redundant assignment
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_flow_cntl.v":310:15:310:23|Removing redundant assignment
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_flow_cntl.v":321:13:321:19|Removing redundant assignment
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_flow_cntl.v":335:18:335:29|Removing redundant assignment
@W: CL169 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_flow_cntl.v":200:0:200:5|Pruning Register intr_req_actv_reg
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_io_cntl.v":39:8:39:19|Synthesizing module isp8_io_cntl
PORT_AW=32'b00000000000000000000000000001000
Generated name = isp8_io_cntl_8s
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":500:7:500:13|Synthesizing module pmi_rom
pmi_addr_depth=32'b00000000000000000000010000000000
pmi_addr_width=32'b00000000000000000000000000001010
pmi_data_width=32'b00000000000000000000000000010010
pmi_regmode=40'b0110111001101111011100100110010101100111
pmi_gsr=56'b01100100011010010111001101100001011000100110110001100101
pmi_resetmode=40'b0110000101110011011110010110111001100011
pmi_init_file=104'b01110000011100100110111101101101010111110110100101101110011010010111010000101110011010000110010101111000
pmi_init_file_format=24'b011010000110010101111000
pmi_family=24'b010110000100111100110010
module_type=56'b01110000011011010110100101011111011100100110111101101101
Generated name = pmi_rom_1024s_10s_18s_noreg_disable_async_prom_init.hex_hex_XO2_pmi_rom_Z2
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":42:7:42:15|Synthesizing module isp8_core
FAMILY_NAME=24'b010110000100111100110010
PROM_FILE=104'b01110000011100100110111101101101010111110110100101101110011010010111010000101110011010000110010101111000
PORT_AW=32'b00000000000000000000000000001000
EXT_AW=32'b00000000000000000000000000011000
PROM_AW=32'b00000000000000000000000000001010
PROM_AD=32'b00000000000000000000010000000000
REGISTERS_16=32'b00000000000000000000000000000000
PGM_STACK_AW=32'b00000000000000000000000000000100
PGM_STACK_AD=32'b00000000000000000000000000010000
REG14=5'b01110
REG15=5'b01111
Generated name = isp8_core_Z3
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":323:28:323:36|Removing redundant assignment
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":335:28:335:36|Removing redundant assignment
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":476:7:476:27|Synthesizing module pmi_distributed_dpram
pmi_addr_depth=32'b00000000000000000000000000100000
pmi_addr_width=32'b00000000000000000000000000000101
pmi_data_width=32'b00000000000000000000000000001000
pmi_regmode=40'b0110111001101111011100100110010101100111
pmi_init_file=32'b01101110011011110110111001100101
pmi_init_file_format=48'b011000100110100101101110011000010111001001111001
pmi_family=24'b010110000100111100110010
module_type=168'b011100000110110101101001010111110110010001101001011100110111010001110010011010010110001001110101011101000110010101100100010111110110010001110000011100100110000101101101
Generated name = pmi_distributed_dpram_32s_5s_8s_noreg_none_binary_XO2_pmi_distributed_dpram_Z4
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\lm8_top.v":142:7:142:27|Synthesizing module pmi_distributed_spram
pmi_addr_depth=32'b00000000000000000000000000100000
pmi_addr_width=32'b00000000000000000000000000000101
pmi_data_width=32'b00000000000000000000000000001000
pmi_regmode=40'b0110111001101111011100100110010101100111
pmi_init_file=32'b01101110011011110110111001100101
pmi_init_file_format=48'b011000100110100101101110011000010111001001111001
pmi_family=24'b010110000100111100110010
module_type=168'b011100000110110101101001010111110110010001101001011100110111010001110010011010010110001001110101011101000110010101100100010111110111001101110000011100100110000101101101
Generated name = pmi_distributed_spram_32s_5s_8s_noreg_none_binary_XO2_pmi_distributed_spram_Z5
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\lm8_top.v":46:7:46:10|Synthesizing module isp8
FAMILY_NAME=24'b010110000100111100110010
PROM_FILE=104'b01110000011100100110111101101101010111110110100101101110011010010111010000101110011010000110010101111000
PORT_AW=32'b00000000000000000000000000001000
EXT_AW=32'b00000000000000000000000000011000
PROM_AW=32'b00000000000000000000000000001010
PROM_AD=32'b00000000000000000000010000000000
REGISTERS_16=32'b00000000000000000000000000000000
PGM_STACK_AW=32'b00000000000000000000000000000100
PGM_STACK_AD=32'b00000000000000000000000000010000
Generated name = isp8_XO2_prom_init.hex_8s_24s_10s_1024s_0s_4s_16s_Z6
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":51:7:51:13|Synthesizing module intface
CLK_IN_MHZ=32'b00000000000000000000000000011000
BAUD_RATE=32'b00000000000000011100001000000000
ADDRWIDTH=32'b00000000000000000000000000000011
DATAWIDTH=32'b00000000000000000000000000001000
FIFO=32'b00000000000000000000000000000000
A_RBR=3'b000
A_THR=3'b000
A_IER=3'b001
A_IIR=3'b010
A_LCR=3'b011
A_LSR=3'b101
A_DIV=3'b111
A_MSR=5'b11000
A_MCR=5'b10000
idle=3'b000
int0=3'b001
int1=3'b010
int2=3'b011
int3=3'b100
Generated name = intface_Z7
@W: CG360 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":108:12:108:25|No assignment to wire fifo_empty_thr
@W: CG360 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":156:27:156:34|No assignment to wire thr_fifo
@W: CG133 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":185:7:185:25|No assignment to iir_rd_strobe_delay
@W: CG133 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":189:7:189:12|No assignment to lsr2_r
@W: CG133 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":189:15:189:20|No assignment to lsr3_r
@W: CG133 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":189:23:189:28|No assignment to lsr4_r
@W: CG133 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":208:15:208:34|No assignment to msr_rd_strobe_detect
@W: CG360 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":212:16:212:28|No assignment to wire fifo_full_thr
@W: CG360 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":214:16:214:35|No assignment to wire fifo_almost_full_thr
@W: CG360 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":215:16:215:36|No assignment to wire fifo_almost_empty_thr
@W: CG360 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":216:16:216:27|No assignment to wire fifo_din_thr
@W: CG133 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":217:16:217:26|No assignment to fifo_wr_thr
@W: CG133 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":218:16:218:28|No assignment to fifo_wr_q_thr
@W: CG360 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":219:16:219:32|No assignment to wire fifo_wr_pulse_thr
@W: CL113 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":351:4:351:9|Feedback mux created for signal mcr[1:0].
@W: CL251 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":351:4:351:9|All reachable assignments to mcr[1:0] assign 0, register removed by optimization
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":49:7:49:12|Synthesizing module rxcver
DATAWIDTH=32'b00000000000000000000000000001000
FIFO=32'b00000000000000000000000000000000
idle=3'b000
shift=3'b001
parity=3'b010
stop=3'b011
idle1=3'b100
lat_family=16'b0101100001001111
Generated name = rxcver_8s_0s_0_1_2_3_4_XO
@W: CG360 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":89:26:89:33|No assignment to wire rbr_fifo
@W: CG360 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":96:27:96:36|No assignment to wire fifo_empty
@W: CG360 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":97:27:97:42|No assignment to wire fifo_almost_full
@W: CG133 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":106:25:106:29|No assignment to count
@W: CG133 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":118:13:118:20|No assignment to rxclk_en
@W: CG360 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":121:26:121:39|No assignment to wire rbr_fifo_error
@W: CG360 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":135:16:135:24|No assignment to wire fifo_full
@W: CG360 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":138:16:138:32|No assignment to wire fifo_almost_empty
@W: CG133 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":139:16:139:23|No assignment to fifo_din
@W: CG133 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":140:16:140:22|No assignment to fifo_wr
@W: CG133 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":141:16:141:24|No assignment to fifo_wr_q
@W: CG360 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":142:16:142:28|No assignment to wire fifo_wr_pulse
@N: CL177 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":426:3:426:8|Sharing sequential element sin_d0_delay.
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\txmitt.v":48:7:48:12|Synthesizing module txmitt
DATAWIDTH=32'b00000000000000000000000000001000
FIFO=32'b00000000000000000000000000000000
start=3'b000
shift=3'b001
parity=3'b010
stop_1bit=3'b011
stop_2bit=3'b100
stop_halfbit=3'b101
start1=3'b110
Generated name = txmitt_8s_0s_0_1_2_3_4_5_6
@W: CG133 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\txmitt.v":92:27:92:39|No assignment to tx_in_start_s
@W: CG133 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\txmitt.v":97:27:97:35|No assignment to txclk_ena
@W: CG133 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\txmitt.v":98:27:98:35|No assignment to txclk_enb
@W: CG133 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\txmitt.v":100:27:100:33|No assignment to count_v
@W: CG133 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\txmitt.v":101:27:101:36|No assignment to thr_rd_int
@W: CG133 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\txmitt.v":102:27:102:38|No assignment to thr_rd_delay
@W: CG133 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\txmitt.v":103:27:103:35|No assignment to last_word
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\modem.v":49:7:49:11|Synthesizing module modem
DATAWIDTH=32'b00000000000000000000000000001000
Generated name = modem_8s
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\uart_core.v":52:7:52:15|Synthesizing module uart_core
CLK_IN_MHZ=32'b00000000000000000000000000011000
BAUD_RATE=32'b00000000000000011100001000000000
ADDRWIDTH=32'b00000000000000000000000000000011
DATAWIDTH=32'b00000000000000000000000000001000
FIFO=32'b00000000000000000000000000000000
Generated name = uart_core_24s_115200s_3s_8s_0s
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_byte_ctrl.v":112:7:112:26|Synthesizing module i2c_master_byte_ctrl
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_bit_ctrl.v":167:7:167:25|Synthesizing module i2c_master_bit_ctrl
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_bit_ctrl.v":252:22:252:24|Removing redundant assignment
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_bit_ctrl.v":415:31:415:37|Removing redundant assignment
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_bit_ctrl.v":416:31:416:37|Removing redundant assignment
@N: CG179 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_bit_ctrl.v":424:31:424:37|Removing redundant assignment
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_registers.v":77:7:77:26|Synthesizing module i2c_master_registers
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_wb_top.v":115:7:115:23|Synthesizing module i2c_master_wb_top
ARST_LVL=1'b1
Generated name = i2c_master_wb_top_1
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1044\Source\Spi_wb.v":48:7:48:9|Synthesizing module spi
SHIFT_DIRECTION=32'b00000000000000000000000000000000
CLOCK_PHASE=32'b00000000000000000000000000000000
CLOCK_POLARITY=32'b00000000000000000000000000000000
CLOCK_SEL=32'b00000000000000000000000000000001
MASTER=32'b00000000000000000000000000000001
SLAVE_NUMBER=32'b00000000000000000000000000000001
DATA_LENGTH=32'b00000000000000000000000000001000
DELAY_TIME=32'b00000000000000000000000000000010
CLKCNT_WIDTH=32'b00000000000000000000000000000101
INTERVAL_LENGTH=32'b00000000000000000000000000000010
UDLY=32'b00000000000000000000000000000001
ST_IDLE=3'b000
ST_LOAD=3'b001
ST_WAIT=3'b010
ST_TRANS=3'b011
ST_TURNAROUND=3'b100
ST_INTERVAL=3'b101
Generated name = spi_Z8
@W: CG133 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1044\Source\Spi_wb.v":133:27:133:36|No assignment to MISO_SLAVE
@W: CL190 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1044\Source\Spi_wb.v":424:4:424:9|Optimizing register bit genblk19.genblk20.tx_shift_data[0] to a constant 0
@W: CL260 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1044\Source\Spi_wb.v":424:4:424:9|Pruning Register bit 0 of genblk19.genblk20.tx_shift_data[7:0]
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":500:7:500:13|Synthesizing module pmi_rom
pmi_addr_depth=32'b00000000000000000000010000000000
pmi_addr_width=32'b00000000000000000000000000001010
pmi_data_width=32'b00000000000000000000000000001000
pmi_regmode=40'b0110111001101111011100100110010101100111
pmi_gsr=56'b01100100011010010111001101100001011000100110110001100101
pmi_resetmode=32'b01110011011110010110111001100011
pmi_init_file=64'b0110110101100101011011100111010100101110011010000110010101111000
pmi_init_file_format=24'b011010000110010101111000
pmi_family=16'b0101100001001111
module_type=56'b01110000011011010110100101011111011100100110111101101101
Generated name = pmi_rom_1024s_10s_8s_noreg_disable_sync_menu.hex_hex_XO_pmi_rom_Z9
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\rom_ebr_wb.v":45:7:45:16|Synthesizing module rom_ebr_wb
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\audio_buffer.v":58:7:58:17|Synthesizing module pmi_fifo_dc
pmi_data_width_w=32'b00000000000000000000000000001000
pmi_data_width_r=32'b00000000000000000000000000001000
pmi_data_depth_w=32'b00000000000000000000000001000000
pmi_data_depth_r=32'b00000000000000000000000001000000
pmi_full_flag=32'b00000000000000000000000001000000
pmi_empty_flag=32'b00000000000000000000000000000000
pmi_almost_full_flag=32'b00000000000000000000000000111100
pmi_almost_empty_flag=32'b00000000000000000000000000000100
pmi_regmode=40'b0110111001101111011100100110010101100111
pmi_resetmode=32'b01110011011110010110111001100011
pmi_family=16'b0101100001001111
module_type=88'b0111000001101101011010010101111101100110011010010110011001101111010111110110010001100011
pmi_implementation=24'b010011000101010101010100
Generated name = pmi_fifo_dc_Z10
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\audio_buffer.v":2:7:2:21|Synthesizing module audio_buffer_wb
FIFO_DEPTH=32'b00000000000000000000000001000000
Generated name = audio_buffer_wb_64s
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\clk_gen.v":3:7:3:19|Synthesizing module audio_clk_gen
CLK_IN_HZ=32'b00000011101110011010110010100000
SAMPLE_CLK_OUT_HZ=32'b00000000000000000011111010000000
COUNT_MAX=32'b00000000000000000000000000000111
Generated name = audio_clk_gen_62500000s_16000s_7s
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\wave_read.v":56:7:56:15|Synthesizing module read_wave
@N: CG364 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\xo_control_soc_demo.v":45:7:45:22|Synthesizing module xo_mini_soc_demo
@W: CS149 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\xo_control_soc_demo.v":308:7:308:14|Port width mismatch for port sw. Formal has width 8, Actual 9
@W: CS149 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\xo_control_soc_demo.v":309:7:309:9|Port width mismatch for port led. Formal has width 8, Actual 4
@W: CG781 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\xo_control_soc_demo.v":343:8:343:8|Undriven input rst_i on instance adc_wb_inst, tying to 0
@W: CG781 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\xo_control_soc_demo.v":344:8:344:8|Undriven input dat_i on instance adc_wb_inst, tying to 0
@W: CG781 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\xo_control_soc_demo.v":346:8:346:8|Undriven input cyc_i on instance adc_wb_inst, tying to 0
@W: CG781 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\xo_control_soc_demo.v":347:7:347:7|Undriven input we_i on instance adc_wb_inst, tying to 0
@W: CG781 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\xo_control_soc_demo.v":392:0:392:8|Undriven input DCD_N on instance UART_INST, tying to 0
@W: CG781 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\xo_control_soc_demo.v":392:0:392:8|Undriven input CTS_N on instance UART_INST, tying to 0
@W: CG781 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\xo_control_soc_demo.v":392:0:392:8|Undriven input DSR_N on instance UART_INST, tying to 0
@W: CG781 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\xo_control_soc_demo.v":392:0:392:8|Undriven input RI_N on instance UART_INST, tying to 0
@W: CG360 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\xo_control_soc_demo.v":148:5:148:16|No assignment to wire audio_readen
@W: CL190 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\clk_gen.v":16:0:16:5|Optimizing register bit clk_count[3] to a constant 0
@W: CL190 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\clk_gen.v":16:0:16:5|Optimizing register bit clk_count[4] to a constant 0
@W: CL190 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\clk_gen.v":16:0:16:5|Optimizing register bit clk_count[5] to a constant 0
@W: CL190 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\clk_gen.v":16:0:16:5|Optimizing register bit clk_count[6] to a constant 0
@W: CL190 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\clk_gen.v":16:0:16:5|Optimizing register bit clk_count[7] to a constant 0
@W: CL190 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\clk_gen.v":16:0:16:5|Optimizing register bit clk_count[8] to a constant 0
@W: CL190 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\clk_gen.v":16:0:16:5|Optimizing register bit clk_count[9] to a constant 0
@W: CL190 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\clk_gen.v":16:0:16:5|Optimizing register bit clk_count[10] to a constant 0
@W: CL190 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\clk_gen.v":16:0:16:5|Optimizing register bit clk_count[11] to a constant 0
@W: CL190 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\clk_gen.v":16:0:16:5|Optimizing register bit clk_count[12] to a constant 0
@W: CL190 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\clk_gen.v":16:0:16:5|Optimizing register bit clk_count[13] to a constant 0
@W: CL260 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\clk_gen.v":16:0:16:5|Pruning Register bit 13 of clk_count[13:0]
@W: CL260 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\clk_gen.v":16:0:16:5|Pruning Register bit 12 of clk_count[13:0]
@W: CL260 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\clk_gen.v":16:0:16:5|Pruning Register bit 11 of clk_count[13:0]
@W: CL260 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\clk_gen.v":16:0:16:5|Pruning Register bit 10 of clk_count[13:0]
@W: CL260 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\clk_gen.v":16:0:16:5|Pruning Register bit 9 of clk_count[13:0]
@W: CL260 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\clk_gen.v":16:0:16:5|Pruning Register bit 8 of clk_count[13:0]
@W: CL260 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\clk_gen.v":16:0:16:5|Pruning Register bit 7 of clk_count[13:0]
@W: CL260 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\clk_gen.v":16:0:16:5|Pruning Register bit 6 of clk_count[13:0]
@W: CL260 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\clk_gen.v":16:0:16:5|Pruning Register bit 5 of clk_count[13:0]
@W: CL260 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\clk_gen.v":16:0:16:5|Pruning Register bit 4 of clk_count[13:0]
@W: CL260 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\clk_gen.v":16:0:16:5|Pruning Register bit 3 of clk_count[13:0]
@W: CL169 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1044\Source\Spi_wb.v":413:3:413:8|Pruning Register genblk19.genblk20.wait_one_tick_done
@A: CL153 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1044\Source\Spi_wb.v":133:27:133:36|*Unassigned bits of MISO_SLAVE have been referenced and are being tied to 0 - simulation mismatch possible
@W: CL159 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1044\Source\Spi_wb.v":95:23:95:31|Input SPI_SEL_I is unused
@W: CL159 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1044\Source\Spi_wb.v":96:23:96:31|Input SPI_CTI_I is unused
@W: CL159 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1044\Source\Spi_wb.v":97:23:97:31|Input SPI_BTE_I is unused
@W: CL159 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1044\Source\Spi_wb.v":98:23:98:32|Input SPI_LOCK_I is unused
@W: CL159 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1044\Source\Spi_wb.v":111:23:111:32|Input MOSI_SLAVE is unused
@W: CL159 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1044\Source\Spi_wb.v":112:23:112:32|Input SS_N_SLAVE is unused
@W: CL159 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1044\Source\Spi_wb.v":113:23:113:32|Input SCLK_SLAVE is unused
@N: CL201 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_bit_ctrl.v":372:1:372:6|Trying to extract state machine for register c_state
Extracted state machine for register c_state
State machine has 18 reachable states with original encodings of:
00000000000000000
00000000000000001
00000000000000010
00000000000000100
00000000000001000
00000000000010000
00000000000100000
00000000001000000
00000000010000000
00000000100000000
00000001000000000
00000010000000000
00000100000000000
00001000000000000
00010000000000000
00100000000000000
01000000000000000
10000000000000000
@N: CL201 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_byte_ctrl.v":246:1:246:6|Trying to extract state machine for register c_state
Extracted state machine for register c_state
State machine has 6 reachable states with original encodings of:
00000
00001
00010
00100
01000
10000
@W: CL159 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_byte_ctrl.v":128:14:128:20|Input clk_cnt is unused
@W: CL159 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\uart_core.v":110:22:110:31|Input UART_CTI_I is unused
@N: CL201 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\modem.v":99:2:99:7|Trying to extract state machine for register msr_reg
@N: CL201 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\txmitt.v":275:3:275:8|Trying to extract state machine for register genblk83.genblk85.tx_state
Extracted state machine for register genblk83.genblk85.tx_state
State machine has 7 reachable states with original encodings of:
000
001
010
011
100
101
110
@W: CL159 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\txmitt.v":79:27:79:40|Input fifo_empty_thr is unused
@N: CL201 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":269:3:269:8|Trying to extract state machine for register cs_state
Extracted state machine for register cs_state
State machine has 5 reachable states with original encodings of:
000
001
010
011
100
@W: CL157 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":89:26:89:33|*Output rbr_fifo has undriven bits - a simulation mismatch is possible
@W: CL157 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":96:27:96:36|*Output fifo_empty has undriven bits - a simulation mismatch is possible
@W: CL157 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":97:27:97:42|*Output fifo_almost_full has undriven bits - a simulation mismatch is possible
@N: CL201 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":575:3:575:8|Trying to extract state machine for register genblk68.genblk70.cs_state
Extracted state machine for register genblk68.genblk70.cs_state
State machine has 5 reachable states with original encodings of:
000
001
010
011
100
@W: CL246 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":112:16:112:20|Input port bits 7 to 3 of adr_i[7:0] are unused
@W: CL246 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":146:28:146:30|Input port bits 7 to 4 of msr[7:0] are unused
@W: CL157 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":108:12:108:25|*Output fifo_empty_thr has undriven bits - a simulation mismatch is possible
@W: CL159 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":117:17:117:21|Input sel_i is unused
@W: CL159 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":118:17:118:21|Input bte_i is unused
@W: CL159 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":120:25:120:32|Input rbr_fifo is unused
@W: CL159 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":109:12:109:21|Input fifo_empty is unused
@W: CL159 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":111:12:111:17|Input thr_rd is unused
@W: CL159 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":110:12:110:27|Input fifo_almost_full is unused
@W: CL246 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_alu.v":59:13:59:17|Input port bits 13 to 2 of instr[17:0] are unused
@A: CL153 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\adc_wb.v":54:19:54:21|*Unassigned bits of led[7:0] have been referenced and are being tied to 0 - simulation mismatch possible
@W: CL159 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\adc_wb.v":48:8:48:12|Input rst_i is unused
@W: CL159 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\adc_wb.v":49:14:49:18|Input dat_i is unused
@W: CL159 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\adc_wb.v":51:8:51:12|Input cyc_i is unused
@W: CL159 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\adc_wb.v":52:8:52:11|Input we_i is unused
@W: CL159 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":13:16:13:29|Input cmd_control_wb is unused
@W: CL159 :"C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\cmd_phy.v":7:6:7:9|Input we_i is unused
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Oct 04 16:26:26 2010
###########################################################]
Synopsys Generic Technology Mapper, Version map520lat, Build 096R, Built Sep 8 2010 10:44:37
Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved
Product Version D-2010.03L-SP1
@N: MF249 |Running in 32-bit mode.
@N: MF257 |Gated clock conversion enabled
@N|Running in logic synthesis mode without enhanced optimization
Finished Timing Extraction Phase. (Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 79MB)
Automatic dissolve during optimization of view:work.adc_wb(verilog) of adc_inst(ADC_top)
@W: MO111 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":108:12:108:25|tristate driver fifo_empty_thr on net fifo_empty_thr has its enable tied to GND (module intface_Z7)
@W: MO111 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":89:26:89:33|tristate driver rbr_fifo_8 on net rbr_fifo_8 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO)
@W: MO111 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":89:26:89:33|tristate driver rbr_fifo_7 on net rbr_fifo_7 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO)
@W: MO111 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":89:26:89:33|tristate driver rbr_fifo_6 on net rbr_fifo_6 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO)
@W: MO111 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":89:26:89:33|tristate driver rbr_fifo_5 on net rbr_fifo_5 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO)
@W: MO111 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":89:26:89:33|tristate driver rbr_fifo_4 on net rbr_fifo_4 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO)
@W: MO111 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":89:26:89:33|tristate driver rbr_fifo_3 on net rbr_fifo_3 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO)
@W: MO111 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":89:26:89:33|tristate driver rbr_fifo_2 on net rbr_fifo_2 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO)
@W: MO111 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":89:26:89:33|tristate driver rbr_fifo_1 on net rbr_fifo_1 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO)
@W: MO111 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":96:27:96:36|tristate driver fifo_empty on net fifo_empty has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO)
@W: MO111 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":97:27:97:42|tristate driver fifo_almost_full on net fifo_almost_full has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO)
@W: MO111 :|tristate driver fifo_empty_thr_t on net fifo_empty_thr has its enable tied to GND (module uart_core_24s_115200s_3s_8s_0s)
@W: MO111 :|tristate driver fifo_empty_t on net fifo_empty has its enable tied to GND (module uart_core_24s_115200s_3s_8s_0s)
@W: MO111 :|tristate driver fifo_almost_full_t on net fifo_almost_full has its enable tied to GND (module uart_core_24s_115200s_3s_8s_0s)
@W: MO111 :|tristate driver RBR_FIFO_t[7] on net RBR_FIFO[7] has its enable tied to GND (module uart_core_24s_115200s_3s_8s_0s)
@W: MO111 :|tristate driver RBR_FIFO_t[6] on net RBR_FIFO[6] has its enable tied to GND (module uart_core_24s_115200s_3s_8s_0s)
@W: MO111 :|tristate driver RBR_FIFO_t[5] on net RBR_FIFO[5] has its enable tied to GND (module uart_core_24s_115200s_3s_8s_0s)
@W: MO111 :|tristate driver RBR_FIFO_t[4] on net RBR_FIFO[4] has its enable tied to GND (module uart_core_24s_115200s_3s_8s_0s)
@W: MO111 :|tristate driver RBR_FIFO_t[3] on net RBR_FIFO[3] has its enable tied to GND (module uart_core_24s_115200s_3s_8s_0s)
@W: MO111 :|tristate driver RBR_FIFO_t[2] on net RBR_FIFO[2] has its enable tied to GND (module uart_core_24s_115200s_3s_8s_0s)
@W: MO111 :|tristate driver RBR_FIFO_t[1] on net RBR_FIFO[1] has its enable tied to GND (module uart_core_24s_115200s_3s_8s_0s)
@W: MO111 :|tristate driver RBR_FIFO_t[0] on net RBR_FIFO[0] has its enable tied to GND (module uart_core_24s_115200s_3s_8s_0s)
Automatic dissolve at startup in view:work.CMD_PHY(verilog) of CRC7_RES_I0(CRC7)
Automatic dissolve at startup in view:work.CMD_PHY(verilog) of CRC7_CMD_I0(CRC7)
Automatic dissolve at startup in view:work.DATA_PHY(verilog) of CRC16_i3(CRC16)
Automatic dissolve at startup in view:work.DATA_PHY(verilog) of CRC16_i2(CRC16)
Automatic dissolve at startup in view:work.DATA_PHY(verilog) of CRC16_i1(CRC16)
Automatic dissolve at startup in view:work.DATA_PHY(verilog) of CRC16_i0(CRC16)
Automatic dissolve at startup in view:work.SD_CORE(verilog) of DATA_PHY_i0(DATA_PHY)
Automatic dissolve at startup in view:work.SD_CORE(verilog) of CMD_PHY_i0(CMD_PHY)
Automatic dissolve at startup in view:work.sigmadelta_adc_8s_10s_3s(verilog) of box_ave(box_ave_8s_3s)
Automatic dissolve at startup in view:work.isp8_core_Z3(verilog) of u1_isp8_io_cntl(isp8_io_cntl_8s)
Automatic dissolve at startup in view:work.isp8_core_Z3(verilog) of u1_isp8_idec(isp8_idec_10s)
Automatic dissolve at startup in view:work.uart_core_24s_115200s_3s_8s_0s(verilog) of u_modem(modem_8s)
Automatic dissolve at startup in view:work.xo_mini_soc_demo(verilog) of WAVE_PROCESSOR(read_wave)
Automatic dissolve at startup in view:work.xo_mini_soc_demo(verilog) of AUDIO_CLK_GEN_INST(audio_clk_gen_62500000s_16000s_7s)
Automatic dissolve at startup in view:work.xo_mini_soc_demo(verilog) of AUDIO_BUFFER_INST(audio_buffer_wb_64s)
Automatic dissolve at startup in view:work.xo_mini_soc_demo(verilog) of STRING_TABLE_INST(rom_ebr_wb)
Automatic dissolve at startup in view:work.xo_mini_soc_demo(verilog) of lm8_wb_inst(lm8_wb_24s_4s_20s_16s)
Automatic dissolve at startup in view:work.xo_mini_soc_demo(verilog) of led_sw_inst(led_sw_wb)
Automatic dissolve at startup in view:work.xo_mini_soc_demo(verilog) of reset_gen_inst(reset_gen)
@N: BN116 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_flow_cntl.v":314:0:314:5|Removing sequential instance ie_flag of view:PrimLib.dffre(prim) because there are no references to its outputs
@N: BN116 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\modem.v":99:2:99:7|Removing sequential instance u_modem.rin_d1 of view:PrimLib.dffs(prim) because there are no references to its outputs
@W: BN132 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\modem.v":99:2:99:7|Removing sequential instance UART_INST.u_modem.dcdn_d1, because it is equivalent to instance UART_INST.u_modem.dsrn_d1
@W: BN132 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\modem.v":99:2:99:7|Removing sequential instance UART_INST.u_modem.ctsn_d1, because it is equivalent to instance UART_INST.u_modem.dsrn_d1
Available hyper_sources - for debug and ip models
None Found
Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 79MB)
@N: BN116 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\led_sw_wb.v":59:0:59:5|Removing sequential instance led_sw_inst.led[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\led_sw_wb.v":59:0:59:5|Removing sequential instance led_sw_inst.led[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\led_sw_wb.v":59:0:59:5|Removing sequential instance led_sw_inst.led[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\led_sw_wb.v":59:0:59:5|Removing sequential instance led_sw_inst.led[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N:"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\wave_read.v":70:1:70:6|Found counter in view:work.xo_mini_soc_demo(verilog) inst WAVE_PROCESSOR.cnt[7:0]
@N:"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\clk_gen.v":35:0:35:5|Found counter in view:work.xo_mini_soc_demo(verilog) inst AUDIO_CLK_GEN_INST.sample_clk_count[7:0]
@N:"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\clk_gen.v":16:0:16:5|Found counter in view:work.xo_mini_soc_demo(verilog) inst AUDIO_CLK_GEN_INST.clk_count[2:0]
@N:"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\reset_gen.v":63:0:63:5|Found counter in view:work.xo_mini_soc_demo(verilog) inst reset_gen_inst.reset_counter[15:0]
@N:"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\sd_core.v":162:0:162:5|Found counter in view:work.SD_CORE(verilog) inst init_clk[5:0]
@N:"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":264:0:264:5|Found counter in view:work.SD_CORE(verilog) inst DATA_PHY_i0.crc16_count[4:0]
@W: BN132 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":358:0:358:5|Removing instance SD_CORE_i0.DATA_PHY_i0.crc16_load[1], because it is equivalent to instance SD_CORE_i0.DATA_PHY_i0.pause_crc16_load
@N: MF179 :|Found 8 bit by 8 bit '==' comparator, 'CMD_PHY_i0.res_done8'
@N: MF179 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\cmd_phy.v":389:36:389:56|Found 7 bit by 7 bit '==' comparator, 'CMD_PHY_i0.un1_res_crc'
@N:"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1066\source\verilog\sigmadelta_adc.v":124:0:124:5|Found counter in view:work.sigmadelta_adc_8s_10s_3s(verilog) inst sigma[9:0]
@N:"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1066\source\verilog\sigmadelta_adc.v":172:0:172:5|Found counter in view:work.sigmadelta_adc_8s_10s_3s(verilog) inst counter[9:0]
@N:"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1066\source\verilog\box_ave.v":131:0:131:5|Found counter in view:work.sigmadelta_adc_8s_10s_3s(verilog) inst box_ave.count[2:0]
@N: FX404 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1066\source\verilog\box_ave.v":152:12:152:13|Found addmux in view:work.sigmadelta_adc_8s_10s_3s(verilog) inst box_ave.accum_4[10:0] from box_ave.un6_accum[10:0]
@W: BN132 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\modem.v":99:2:99:7|Removing instance UART_INST.u_modem.msr_reg[0], because it is equivalent to instance UART_INST.u_modem.msr_reg[1]
@W: BN132 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\modem.v":99:2:99:7|Removing instance UART_INST.u_modem.msr_reg[3], because it is equivalent to instance UART_INST.u_modem.msr_reg[1]
@W: BN132 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\modem.v":99:2:99:7|Removing instance UART_INST.u_modem.msr_reg[6], because it is equivalent to instance UART_INST.u_modem.msr_reg[7]
@W: BN132 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\modem.v":99:2:99:7|Removing instance UART_INST.u_modem.msr_reg[5], because it is equivalent to instance UART_INST.u_modem.msr_reg[7]
@W: BN132 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\modem.v":99:2:99:7|Removing instance UART_INST.u_modem.msr_reg[4], because it is equivalent to instance UART_INST.u_modem.msr_reg[7]
Encoding state machine work.intface_Z7(verilog)-genblk68\.genblk70\.cs_state[4:0]
original code -> new code
000 -> 00001
001 -> 00010
010 -> 00100
011 -> 01000
100 -> 10000
@W: BN132 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":223:3:223:8|Removing instance UART_INST.u_intface.divisor[14], because it is equivalent to instance UART_INST.u_intface.divisor[15]
@W: BN132 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":223:3:223:8|Removing instance UART_INST.u_intface.divisor[13], because it is equivalent to instance UART_INST.u_intface.divisor[15]
@W: BN132 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":223:3:223:8|Removing instance UART_INST.u_intface.divisor[12], because it is equivalent to instance UART_INST.u_intface.divisor[15]
@W: BN132 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":223:3:223:8|Removing instance UART_INST.u_intface.divisor[11], because it is equivalent to instance UART_INST.u_intface.divisor[15]
@W: BN132 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":223:3:223:8|Removing instance UART_INST.u_intface.divisor[10], because it is equivalent to instance UART_INST.u_intface.divisor[15]
@W: BN132 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":223:3:223:8|Removing instance UART_INST.u_intface.divisor[9], because it is equivalent to instance UART_INST.u_intface.divisor[15]
@W: BN132 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":223:3:223:8|Removing instance UART_INST.u_intface.divisor[8], because it is equivalent to instance UART_INST.u_intface.divisor[15]
@N: BN116 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\intface.v":223:3:223:8|Removing sequential instance divisor[15] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
Encoding state machine work.rxcver_8s_0s_0_1_2_3_4_XO(verilog)-cs_state[4:0]
original code -> new code
000 -> 00001
001 -> 00010
010 -> 00100
011 -> 01000
100 -> 10000
@N:"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":269:3:269:8|Found counter in view:work.rxcver_8s_0s_0_1_2_3_4_XO(verilog) inst databit_recved_num[3:0]
@N: FX404 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":278:13:278:16|Found addmux in view:work.rxcver_8s_0s_0_1_2_3_4_XO(verilog) inst counter_11[15:0] from un1_counter_2[15:0]
@N: MF179 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\rxcver.v":286:10:286:30|Found 16 bit by 16 bit '==' comparator, 'cs_state13'
Encoding state machine work.txmitt_8s_0s_0_1_2_3_4_5_6(verilog)-genblk83\.genblk85\.tx_state[6:0]
original code -> new code
000 -> 0000001
001 -> 0000010
010 -> 0000100
011 -> 0001000
100 -> 0010000
101 -> 0100000
110 -> 1000000
@N:"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\txmitt.v":275:3:275:8|Found counter in view:work.txmitt_8s_0s_0_1_2_3_4_5_6(verilog) inst genblk83\.genblk85\.counter[15:0]
@N:"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\txmitt.v":275:3:275:8|Found counter in view:work.txmitt_8s_0s_0_1_2_3_4_5_6(verilog) inst genblk83\.genblk85\.tx_cnt[2:0]
@N:"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1044\source\spi_wb.v":334:3:334:8|Found counter in view:work.spi_Z8(verilog) inst genblk19\.genblk20\.clock_cnt[4:0]
Encoding state machine work.i2c_master_byte_ctrl(verilog)-c_state[5:0]
original code -> new code
00000 -> 000001
00001 -> 000010
00010 -> 000100
00100 -> 001000
01000 -> 010000
10000 -> 100000
@N:"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_byte_ctrl.v":229:1:229:6|Found counter in view:work.i2c_master_byte_ctrl(verilog) inst dcnt[2:0]
Encoding state machine work.i2c_master_bit_ctrl(verilog)-c_state[17:0]
original code -> new code
00000000000000000 -> 000000000000000001
00000000000000001 -> 000000000000000010
00000000000000010 -> 000000000000000100
00000000000000100 -> 000000000000001000
00000000000001000 -> 000000000000010000
00000000000010000 -> 000000000000100000
00000000000100000 -> 000000000001000000
00000000001000000 -> 000000000010000000
00000000010000000 -> 000000000100000000
00000000100000000 -> 000000001000000000
00000001000000000 -> 000000010000000000
00000010000000000 -> 000000100000000000
00000100000000000 -> 000001000000000000
00001000000000000 -> 000010000000000000
00010000000000000 -> 000100000000000000
00100000000000000 -> 001000000000000000
01000000000000000 -> 010000000000000000
10000000000000000 -> 100000000000000000
@N:"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_bit_ctrl.v":234:1:234:6|Found counter in view:work.i2c_master_bit_ctrl(verilog) inst cnt[15:0]
@W: BN132 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":451:3:451:8|Removing instance lm8_inst.u1_isp8.din_rd1[0], because it is equivalent to instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[0]
@W: BN132 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":451:3:451:8|Removing instance lm8_inst.u1_isp8.din_rd1[1], because it is equivalent to instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[1]
@W: BN132 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":451:3:451:8|Removing instance lm8_inst.u1_isp8.din_rd1[2], because it is equivalent to instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[2]
@W: BN132 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":451:3:451:8|Removing instance lm8_inst.u1_isp8.din_rd1[3], because it is equivalent to instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[3]
@W: BN132 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":451:3:451:8|Removing instance lm8_inst.u1_isp8.din_rd1[4], because it is equivalent to instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[4]
@W: BN132 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":451:3:451:8|Removing instance lm8_inst.u1_isp8.din_rd1[5], because it is equivalent to instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[5]
@W: BN132 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":451:3:451:8|Removing instance lm8_inst.u1_isp8.din_rd1[6], because it is equivalent to instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[6]
@W: BN132 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":451:3:451:8|Removing instance lm8_inst.u1_isp8.din_rd1[7], because it is equivalent to instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[7]
@N: BN116 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1046\source\i2c_master_wb_top.v":234:1:234:6|Removing sequential instance I2C_INST.wb_inta_o of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1042\source\modem.v":99:2:99:7|Removing sequential instance UART_INST.u_modem.msr_reg[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":316:6:316:11|Removing sequential instance lm8_inst.u1_isp8.genblk9\.genblk10\.page_ptr1[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":316:6:316:11|Removing sequential instance lm8_inst.u1_isp8.genblk9\.genblk10\.page_ptr1[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":316:6:316:11|Removing sequential instance lm8_inst.u1_isp8.genblk9\.genblk10\.page_ptr1[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":316:6:316:11|Removing sequential instance lm8_inst.u1_isp8.genblk9\.genblk10\.page_ptr1[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":316:6:316:11|Removing sequential instance lm8_inst.u1_isp8.genblk9\.genblk10\.page_ptr1[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":316:6:316:11|Removing sequential instance lm8_inst.u1_isp8.genblk9\.genblk10\.page_ptr1[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":328:6:328:11|Removing sequential instance lm8_inst.u1_isp8.genblk11\.genblk12\.page_ptr2[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":328:6:328:11|Removing sequential instance lm8_inst.u1_isp8.genblk11\.genblk12\.page_ptr2[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":328:6:328:11|Removing sequential instance lm8_inst.u1_isp8.genblk11\.genblk12\.page_ptr2[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":328:6:328:11|Removing sequential instance lm8_inst.u1_isp8.genblk11\.genblk12\.page_ptr2[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1066\source\verilog\box_ave.v":108:0:108:5|Removing sequential instance adc_wb_inst.adc_inst.SSD_ADC.box_ave.result_valid of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
Finished factoring (Time elapsed 0h:00m:03s; Memory used current: 92MB peak: 93MB)
@N: BN116 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\sd_core.v":124:0:124:5|Removing sequential instance SD_CORE_i0.control_wb_r_0[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\sd_core.v":124:0:124:5|Removing sequential instance SD_CORE_i0.control_wb_r[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\sd_core.v":124:0:124:5|Removing sequential instance SD_CORE_i0.control_wb_r_2[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\sd_core.v":124:0:124:5|Removing sequential instance SD_CORE_i0.control_wb_r_1[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
#################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[
======================================================================================
Instance:Pin Generated Clock Optimization Status
======================================================================================
SD_CORE_i0.control_wb_r_3[2]:C Not Done
AUDIO_CLK_GEN_INST.clkout:C Not Done
reset_gen_inst.rst2_out:C Not Done
reset_gen_inst.rst1_out:C Not Done
AUDIO_CLK_GEN_INST.clk_count[0]:C Not Done
AUDIO_CLK_GEN_INST.clk_count[2]:C Not Done
AUDIO_CLK_GEN_INST.clk_count[1]:C Not Done
reset_gen_inst.reset_counter[15:0]:C Not Done
AUDIO_CLK_GEN_INST.sample_clk_count[7:0]:C Not Done
WAVE_PROCESSOR.cnt[7:0]:C Done
led_sw_inst.led[3]:C Not Done
led_sw_inst.led[2]:C Not Done
led_sw_inst.led[1]:C Not Done
led_sw_inst.led[0]:C Not Done
lm8_wb_inst.ack_reg:C Not Done
WAVE_PROCESSOR.PWM_reg:C Done
I2C_INST.wb_ack_o:C Not Done
I2C_INST.wb_dat_o[7]:C Not Done
I2C_INST.wb_dat_o[6]:C Not Done
I2C_INST.wb_dat_o[5]:C Not Done
I2C_INST.wb_dat_o[4]:C Not Done
I2C_INST.wb_dat_o[3]:C Not Done
I2C_INST.wb_dat_o[2]:C Not Done
I2C_INST.wb_dat_o[1]:C Not Done
I2C_INST.wb_dat_o[0]:C Not Done
I2C_INST.registers.irq_flag:C Not Done
I2C_INST.registers.tip:C Not Done
I2C_INST.registers.rxack:C Not Done
I2C_INST.registers.al:C Not Done
I2C_INST.registers.ctr[7]:C Not Done
I2C_INST.registers.ctr[6]:C Not Done
I2C_INST.registers.ctr[5]:C Not Done
I2C_INST.registers.ctr[4]:C Not Done
I2C_INST.registers.ctr[3]:C Not Done
I2C_INST.registers.ctr[2]:C Not Done
I2C_INST.registers.ctr[1]:C Not Done
I2C_INST.registers.ctr[0]:C Not Done
I2C_INST.registers.txr[7]:C Not Done
I2C_INST.registers.txr[6]:C Not Done
I2C_INST.registers.txr[5]:C Not Done
I2C_INST.registers.txr[4]:C Not Done
I2C_INST.registers.txr[3]:C Not Done
I2C_INST.registers.txr[2]:C Not Done
I2C_INST.registers.txr[1]:C Not Done
I2C_INST.registers.txr[0]:C Not Done
I2C_INST.registers.cr[7]:C Not Done
I2C_INST.registers.cr[6]:C Not Done
I2C_INST.registers.cr[5]:C Not Done
I2C_INST.registers.cr[4]:C Not Done
I2C_INST.registers.cr[3]:C Not Done
I2C_INST.registers.cr[2]:C Not Done
I2C_INST.registers.cr[1]:C Not Done
I2C_INST.registers.cr[0]:C Not Done
I2C_INST.registers.prer[15]:C Not Done
I2C_INST.registers.prer[14]:C Not Done
I2C_INST.registers.prer[13]:C Not Done
I2C_INST.registers.prer[12]:C Not Done
I2C_INST.registers.prer[11]:C Not Done
I2C_INST.registers.prer[10]:C Not Done
I2C_INST.registers.prer[9]:C Not Done
I2C_INST.registers.prer[8]:C Not Done
I2C_INST.registers.prer[7]:C Not Done
I2C_INST.registers.prer[6]:C Not Done
I2C_INST.registers.prer[5]:C Not Done
I2C_INST.registers.prer[4]:C Not Done
I2C_INST.registers.prer[3]:C Not Done
I2C_INST.registers.prer[2]:C Not Done
I2C_INST.registers.prer[1]:C Not Done
I2C_INST.registers.prer[0]:C Not Done
I2C_INST.bit_controller.sta_condition:C Not Done
I2C_INST.bit_controller.sSDA:C Not Done
I2C_INST.bit_controller.sSCL:C Not Done
I2C_INST.bit_controller.dSDA:C Not Done
I2C_INST.bit_controller.dSCL:C Not Done
I2C_INST.bit_controller.dscl_oen:C Not Done
I2C_INST.bit_controller.cmd_ack:C Not Done
I2C_INST.bit_controller.clk_en:C Not Done
I2C_INST.bit_controller.al:C Not Done
I2C_INST.bit_controller.busy:C Not Done
I2C_INST.bit_controller.sto_condition:C Not Done
I2C_INST.bit_controller.c_state[4]:C Not Done
I2C_INST.bit_controller.c_state[3]:C Not Done
I2C_INST.bit_controller.c_state[2]:C Not Done
I2C_INST.bit_controller.c_state[1]:C Not Done
I2C_INST.bit_controller.c_state_i[0]:C Not Done
I2C_INST.bit_controller.c_state[17]:C Not Done
I2C_INST.bit_controller.c_state[16]:C Not Done
I2C_INST.bit_controller.c_state[15]:C Not Done
I2C_INST.bit_controller.c_state[14]:C Not Done
I2C_INST.bit_controller.c_state[13]:C Not Done
I2C_INST.bit_controller.c_state[12]:C Not Done
I2C_INST.bit_controller.c_state[11]:C Not Done
I2C_INST.bit_controller.c_state[10]:C Not Done
I2C_INST.bit_controller.c_state[9]:C Not Done
I2C_INST.bit_controller.c_state[8]:C Not Done
I2C_INST.bit_controller.c_state[7]:C Not Done
I2C_INST.bit_controller.c_state[6]:C Not Done
I2C_INST.bit_controller.c_state[5]:C Not Done
I2C_INST.bit_controller.cnt[15:0]:C Not Done
I2C_INST.bit_controller.dout:C Not Done
I2C_INST.bit_controller.cmd_stop:C Not Done
I2C_INST.bit_controller.sda_chk:C Not Done
I2C_INST.bit_controller.scl_oen:C Not Done
I2C_INST.bit_controller.sda_oen:C Not Done
I2C_INST.byte_controller.ld:C Not Done
I2C_INST.byte_controller.shift:C Not Done
I2C_INST.byte_controller.core_txd:C Not Done
I2C_INST.byte_controller.cmd_ack:C Not Done
I2C_INST.byte_controller.c_state[4]:C Not Done
I2C_INST.byte_controller.c_state[3]:C Not Done
I2C_INST.byte_controller.c_state[2]:C Not Done
I2C_INST.byte_controller.c_state[1]:C Not Done
I2C_INST.byte_controller.c_state_i[0]:C Not Done
I2C_INST.byte_controller.c_state[5]:C Not Done
I2C_INST.byte_controller.dcnt[1]:C Not Done
I2C_INST.byte_controller.dcnt[0]:C Not Done
I2C_INST.byte_controller.dcnt[2]:C Not Done
I2C_INST.byte_controller.ack_out:C Not Done
I2C_INST.byte_controller.sr[7]:C Not Done
I2C_INST.byte_controller.sr[6]:C Not Done
I2C_INST.byte_controller.sr[5]:C Not Done
I2C_INST.byte_controller.sr[4]:C Not Done
I2C_INST.byte_controller.sr[3]:C Not Done
I2C_INST.byte_controller.sr[2]:C Not Done
I2C_INST.byte_controller.sr[1]:C Not Done
I2C_INST.byte_controller.sr[0]:C Not Done
I2C_INST.byte_controller.core_cmd[3]:C Not Done
I2C_INST.byte_controller.core_cmd[2]:C Not Done
I2C_INST.byte_controller.core_cmd[1]:C Not Done
I2C_INST.byte_controller.core_cmd[0]:C Not Done
SPI_INST.dw10_cs:C Not Done
SPI_INST.dw0c_cs:C Not Done
SPI_INST.dw08_cs:C Not Done
SPI_INST.dw04_cs:C Not Done
SPI_INST.dw00_cs:C Not Done
SPI_INST.reg_rd:C Not Done
SPI_INST.reg_wr:C Not Done
SPI_INST.SS_N_MASTER[0]:C Not Done
SPI_INST.genblk19.genblk20.rx_latch_flag:C Not Done
SPI_INST.SPI_ACK_O:C Not Done
SPI_INST.genblk19.genblk20.reg_tmt:C Not Done
SPI_INST.genblk19.genblk20.data_cnt[2]:C Not Done
SPI_INST.genblk19.genblk20.data_cnt[1]:C Not Done
SPI_INST.genblk19.genblk20.data_cnt[0]:C Not Done
SPI_INST.genblk19.genblk20.c_status[2]:C Not Done
SPI_INST.genblk19.genblk20.c_status[1]:C Not Done
SPI_INST.genblk19.genblk20.c_status[0]:C Not Done
SPI_INST.latch_s_data[7]:C Not Done
SPI_INST.latch_s_data[6]:C Not Done
SPI_INST.latch_s_data[5]:C Not Done
SPI_INST.latch_s_data[4]:C Not Done
SPI_INST.latch_s_data[3]:C Not Done
SPI_INST.latch_s_data[2]:C Not Done
SPI_INST.latch_s_data[1]:C Not Done
SPI_INST.latch_s_data[0]:C Not Done
SPI_INST.genblk19.genblk20.data_cnt[5]:C Not Done
SPI_INST.genblk19.genblk20.data_cnt[4]:C Not Done
SPI_INST.genblk19.genblk20.data_cnt[3]:C Not Done
SPI_INST.genblk19.genblk20.clock_cnt[4:0]:C Not Done
SPI_INST.reg_txdata[7]:C Not Done
SPI_INST.reg_txdata[6]:C Not Done
SPI_INST.reg_txdata[5]:C Not Done
SPI_INST.reg_txdata[4]:C Not Done
SPI_INST.reg_txdata[3]:C Not Done
SPI_INST.reg_txdata[2]:C Not Done
SPI_INST.reg_txdata[1]:C Not Done
SPI_INST.reg_txdata[0]:C Not Done
SPI_INST.reg_ie:C Not Done
SPI_INST.reg_iroe:C Not Done
SPI_INST.reg_irrdy:C Not Done
SPI_INST.reg_itoe:C Not Done
SPI_INST.reg_itrdy:C Not Done
SPI_INST.reg_sso:C Not Done
SPI_INST.genblk19.genblk20.reg_ssmask[0]:C Not Done
SPI_INST.read_wait_done:C Not Done
SPI_INST.genblk19.genblk20.pending_data:C Not Done
SPI_INST.SCLK_MASTER:C Not Done
SPI_INST.genblk19.genblk20.rx_shift_data[7]:C Not Done
SPI_INST.genblk19.genblk20.rx_shift_data[6]:C Not Done
SPI_INST.genblk19.genblk20.rx_shift_data[5]:C Not Done
SPI_INST.genblk19.genblk20.rx_shift_data[4]:C Not Done
SPI_INST.genblk19.genblk20.rx_shift_data[3]:C Not Done
SPI_INST.genblk19.genblk20.rx_shift_data[2]:C Not Done
SPI_INST.genblk19.genblk20.rx_shift_data[1]:C Not Done
SPI_INST.genblk19.genblk20.rx_shift_data[0]:C Not Done
SPI_INST.genblk19.genblk20.reg_toe:C Not Done
SPI_INST.reg_rxdata[7]:C Not Done
SPI_INST.reg_rxdata[6]:C Not Done
SPI_INST.reg_rxdata[5]:C Not Done
SPI_INST.reg_rxdata[4]:C Not Done
SPI_INST.reg_rxdata[3]:C Not Done
SPI_INST.reg_rxdata[2]:C Not Done
SPI_INST.reg_rxdata[1]:C Not Done
SPI_INST.reg_rxdata[0]:C Not Done
SPI_INST.genblk19.genblk20.reg_trdy:C Not Done
SPI_INST.SPI_DAT_O[7]:C Not Done
SPI_INST.SPI_DAT_O[6]:C Not Done
SPI_INST.SPI_DAT_O[5]:C Not Done
SPI_INST.SPI_DAT_O[4]:C Not Done
SPI_INST.SPI_DAT_O[3]:C Not Done
SPI_INST.SPI_DAT_O[2]:C Not Done
SPI_INST.SPI_DAT_O[1]:C Not Done
SPI_INST.SPI_DAT_O[0]:C Not Done
SPI_INST.MOSI_MASTER:C Not Done
SPI_INST.genblk19.genblk20.tx_shift_data[7]:C Not Done
SPI_INST.genblk19.genblk20.tx_shift_data[6]:C Not Done
SPI_INST.genblk19.genblk20.tx_shift_data[5]:C Not Done
SPI_INST.genblk19.genblk20.tx_shift_data[4]:C Not Done
SPI_INST.genblk19.genblk20.tx_shift_data[3]:C Not Done
SPI_INST.genblk19.genblk20.tx_shift_data[2]:C Not Done
SPI_INST.genblk19.genblk20.tx_shift_data[1]:C Not Done
SPI_INST.genblk19.genblk20.reg_roe:C Not Done
SPI_INST.genblk19.genblk20.reg_rrdy:C Not Done
SPI_INST.genblk19.genblk20.n_status[2]:C Not Done
SPI_INST.genblk19.genblk20.n_status[1]:C Not Done
SPI_INST.genblk19.genblk20.n_status[0]:C Not Done
UART_INST.u_modem.msr_reg[2]:C Not Done
UART_INST.u_modem.msr_reg[1]:C Not Done
UART_INST.u_modem.dsrn_d1:C Not Done
UART_INST.u_txmitt.tx_in_stop_s1:C Not Done
UART_INST.u_txmitt.tx_in_shift_s1:C Not Done
UART_INST.u_txmitt.tx_in_stop_s:C Not Done
UART_INST.u_txmitt.tx_in_shift_s:C Not Done
UART_INST.u_txmitt.genblk83.genblk85.tx_state[4]:C Not Done
UART_INST.u_txmitt.genblk83.genblk85.tx_state[3]:C Not Done
UART_INST.u_txmitt.genblk83.genblk85.tx_state[2]:C Not Done
UART_INST.u_txmitt.genblk83.genblk85.tx_state[1]:C Not Done
UART_INST.u_txmitt.genblk83.genblk85.tx_state[0]:C Not Done
UART_INST.u_txmitt.genblk83.genblk85.tx_state[6]:C Not Done
UART_INST.u_txmitt.genblk83.genblk85.tx_state[5]:C Not Done
UART_INST.u_txmitt.genblk83.genblk85.tx_cnt[0]:C Not Done
UART_INST.u_txmitt.genblk83.genblk85.tx_cnt[2]:C Not Done
UART_INST.u_txmitt.genblk83.genblk85.tx_cnt[1]:C Not Done
UART_INST.u_txmitt.genblk83.genblk85.counter[15:0]:C Not Done
UART_INST.u_txmitt.genblk86.genblk88.tsr_empty:C Not Done
UART_INST.u_txmitt.genblk89.genblk91.thr_empty:C Not Done
UART_INST.u_txmitt.genblk83.genblk85.tx_output:C Not Done
UART_INST.u_txmitt.genblk83.genblk85.tx_parity:C Not Done
UART_INST.u_txmitt.genblk83.genblk85.tsr[7]:C Not Done
UART_INST.u_txmitt.genblk83.genblk85.tsr[6]:C Not Done
UART_INST.u_txmitt.genblk83.genblk85.tsr[5]:C Not Done
UART_INST.u_txmitt.genblk83.genblk85.tsr[4]:C Not Done
UART_INST.u_txmitt.genblk83.genblk85.tsr[3]:C Not Done
UART_INST.u_txmitt.genblk83.genblk85.tsr[2]:C Not Done
UART_INST.u_txmitt.genblk83.genblk85.tsr[1]:C Not Done
UART_INST.u_txmitt.genblk83.genblk85.tsr[0]:C Not Done
UART_INST.u_rxcver.sampled_once:C Not Done
UART_INST.u_rxcver.rx_idle_d1:C Not Done
UART_INST.u_rxcver.sin_d1:C Not Done
UART_INST.u_rxcver.rx_frame_err_d1:C Not Done
UART_INST.u_rxcver.sin_d0:C Not Done
UART_INST.u_rxcver.rx_idle:C Not Done
UART_INST.u_rxcver.cs_state[3]:C Not Done
UART_INST.u_rxcver.cs_state[2]:C Not Done
UART_INST.u_rxcver.cs_state[1]:C Not Done
UART_INST.u_rxcver.cs_state[0]:C Not Done
UART_INST.u_rxcver.cs_state[4]:C Not Done
UART_INST.u_rxcver.databit_recved_num[2]:C Not Done
UART_INST.u_rxcver.databit_recved_num[1]:C Not Done
UART_INST.u_rxcver.databit_recved_num[0]:C Not Done
UART_INST.u_rxcver.counter[11]:C Not Done
UART_INST.u_rxcver.counter[10]:C Not Done
UART_INST.u_rxcver.counter[9]:C Not Done
UART_INST.u_rxcver.counter[8]:C Not Done
UART_INST.u_rxcver.counter[7]:C Not Done
UART_INST.u_rxcver.counter[6]:C Not Done
UART_INST.u_rxcver.counter[5]:C Not Done
UART_INST.u_rxcver.counter[4]:C Not Done
UART_INST.u_rxcver.counter[3]:C Not Done
UART_INST.u_rxcver.counter[2]:C Not Done
UART_INST.u_rxcver.counter[1]:C Not Done
UART_INST.u_rxcver.counter[0]:C Not Done
UART_INST.u_rxcver.databit_recved_num[3]:C Not Done
UART_INST.u_rxcver.counter[15]:C Not Done
UART_INST.u_rxcver.counter[14]:C Not Done
UART_INST.u_rxcver.counter[13]:C Not Done
UART_INST.u_rxcver.counter[12]:C Not Done
UART_INST.u_rxcver.genblk72.genblk74.rbr_datardy:C Not Done
UART_INST.u_rxcver.genblk78.genblk80.break_int_int:C Not Done
UART_INST.u_rxcver.genblk78.genblk80.frame_err_int:C Not Done
UART_INST.u_rxcver.genblk78.genblk80.overrun_err_int:C Not Done
UART_INST.u_rxcver.hunt:C Not Done
UART_INST.u_rxcver.genblk78.genblk80.parity_err_int:C Not Done
UART_INST.u_rxcver.rbr[7]:C Not Done
UART_INST.u_rxcver.rbr[6]:C Not Done
UART_INST.u_rxcver.rbr[5]:C Not Done
UART_INST.u_rxcver.rbr[4]:C Not Done
UART_INST.u_rxcver.rbr[3]:C Not Done
UART_INST.u_rxcver.rbr[2]:C Not Done
UART_INST.u_rxcver.rbr[1]:C Not Done
UART_INST.u_rxcver.rbr[0]:C Not Done
UART_INST.u_rxcver.hunt_one:C Not Done
UART_INST.u_rxcver.rx_frame_err:C Not Done
UART_INST.u_rxcver.rsr[7]:C Not Done
UART_INST.u_rxcver.rsr[6]:C Not Done
UART_INST.u_rxcver.rsr[5]:C Not Done
UART_INST.u_rxcver.rsr[4]:C Not Done
UART_INST.u_rxcver.rsr[3]:C Not Done
UART_INST.u_rxcver.rsr[2]:C Not Done
UART_INST.u_rxcver.rsr[1]:C Not Done
UART_INST.u_rxcver.rsr[0]:C Not Done
UART_INST.u_rxcver.rx_parity_err:C Not Done
UART_INST.u_intface.rbr_rd_nonfifo:C Not Done
UART_INST.u_intface.thr_wr:C Not Done
UART_INST.u_intface.ack_o:C Not Done
UART_INST.u_intface.genblk68.genblk70.cs_state[1]:C Not Done
UART_INST.u_intface.genblk68.genblk70.cs_state[0]:C Not Done
UART_INST.u_intface.genblk68.genblk70.cs_state[4]:C Not Done
UART_INST.u_intface.genblk68.genblk70.cs_state[3]:C Not Done
UART_INST.u_intface.genblk68.genblk70.cs_state[2]:C Not Done
UART_INST.u_intface.divisor[7]:C Not Done
UART_INST.u_intface.divisor[6]:C Not Done
UART_INST.u_intface.divisor[5]:C Not Done
UART_INST.u_intface.divisor[4]:C Not Done
UART_INST.u_intface.divisor[3]:C Not Done
UART_INST.u_intface.divisor[2]:C Not Done
UART_INST.u_intface.divisor[1]:C Not Done
UART_INST.u_intface.divisor[0]:C Not Done
UART_INST.u_intface.genblk55.genblk56.thr_nonfifo[7]:C Not Done
UART_INST.u_intface.genblk55.genblk56.thr_nonfifo[6]:C Not Done
UART_INST.u_intface.genblk55.genblk56.thr_nonfifo[5]:C Not Done
UART_INST.u_intface.genblk55.genblk56.thr_nonfifo[4]:C Not Done
UART_INST.u_intface.genblk55.genblk56.thr_nonfifo[3]:C Not Done
UART_INST.u_intface.genblk55.genblk56.thr_nonfifo[2]:C Not Done
UART_INST.u_intface.genblk55.genblk56.thr_nonfifo[1]:C Not Done
UART_INST.u_intface.genblk55.genblk56.thr_nonfifo[0]:C Not Done
UART_INST.u_intface.genblk55.genblk56.ier[3]:C Not Done
UART_INST.u_intface.genblk55.genblk56.ier[2]:C Not Done
UART_INST.u_intface.genblk55.genblk56.ier[1]:C Not Done
UART_INST.u_intface.genblk55.genblk56.ier[0]:C Not Done
UART_INST.u_intface.genblk55.genblk56.lcr[6]:C Not Done
UART_INST.u_intface.genblk55.genblk56.lcr[5]:C Not Done
UART_INST.u_intface.genblk55.genblk56.lcr[4]:C Not Done
UART_INST.u_intface.genblk55.genblk56.lcr[3]:C Not Done
UART_INST.u_intface.genblk55.genblk56.lcr[2]:C Not Done
UART_INST.u_intface.genblk55.genblk56.lcr[1]:C Not Done
UART_INST.u_intface.genblk55.genblk56.lcr[0]:C Not Done
UART_INST.u_intface.genblk52.genblk54.data_8bit[7]:C Not Done
UART_INST.u_intface.genblk52.genblk54.data_8bit[6]:C Not Done
UART_INST.u_intface.genblk52.genblk54.data_8bit[5]:C Not Done
UART_INST.u_intface.genblk52.genblk54.data_8bit[4]:C Not Done
UART_INST.u_intface.genblk52.genblk54.data_8bit[3]:C Not Done
UART_INST.u_intface.genblk52.genblk54.data_8bit[2]:C Not Done
UART_INST.u_intface.genblk52.genblk54.data_8bit[1]:C Not Done
UART_INST.u_intface.genblk52.genblk54.data_8bit[0]:C Not Done
lm8_inst.u1_isp8.u1_isp8_io_cntl.ext_io_rd:C Not Done
lm8_inst.u1_isp8.u1_isp8_io_cntl.ext_mem_wr:C Not Done
lm8_inst.u1_isp8.u1_isp8_io_cntl.ext_mem_rd:C Not Done
lm8_inst.u1_isp8.u1_isp8_io_cntl.ext_io_wr:C Not Done
lm8_inst.u1_isp8.wren_alu_rd:C Not Done
lm8_inst.u1_isp8.wren_il_rd:C Not Done
lm8_inst.u1_isp8.u1_isp8_io_cntl.ext_addr[3]:C Not Done
lm8_inst.u1_isp8.u1_isp8_io_cntl.ext_addr[2]:C Not Done
lm8_inst.u1_isp8.u1_isp8_io_cntl.ext_addr[1]:C Not Done
lm8_inst.u1_isp8.u1_isp8_io_cntl.ext_addr[0]:C Not Done
lm8_inst.u1_isp8.u1_isp8_io_cntl.ext_dout[7]:C Not Done
lm8_inst.u1_isp8.u1_isp8_io_cntl.ext_dout[6]:C Not Done
lm8_inst.u1_isp8.u1_isp8_io_cntl.ext_dout[5]:C Not Done
lm8_inst.u1_isp8.u1_isp8_io_cntl.ext_dout[4]:C Not Done
lm8_inst.u1_isp8.u1_isp8_io_cntl.ext_dout[3]:C Not Done
lm8_inst.u1_isp8.u1_isp8_io_cntl.ext_dout[2]:C Not Done
lm8_inst.u1_isp8.u1_isp8_io_cntl.ext_dout[1]:C Not Done
lm8_inst.u1_isp8.u1_isp8_io_cntl.ext_dout[0]:C Not Done
lm8_inst.u1_isp8.u1_isp8_io_cntl.ext_addr[7]:C Not Done
lm8_inst.u1_isp8.u1_isp8_io_cntl.ext_addr[6]:C Not Done
lm8_inst.u1_isp8.u1_isp8_io_cntl.ext_addr[5]:C Not Done
lm8_inst.u1_isp8.u1_isp8_io_cntl.ext_addr[4]:C Not Done
lm8_inst.u1_isp8.genblk9.genblk10.page_ptr1[1]:C Not Done
lm8_inst.u1_isp8.genblk9.genblk10.page_ptr1[0]:C Not Done
lm8_inst.u1_isp8.genblk11.genblk12.page_ptr2[7]:C Not Done
lm8_inst.u1_isp8.genblk11.genblk12.page_ptr2[6]:C Not Done
lm8_inst.u1_isp8.genblk11.genblk12.page_ptr2[5]:C Not Done
lm8_inst.u1_isp8.genblk11.genblk12.page_ptr2[4]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.data_cyc_int:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.ext_addr_cyc_int:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.addr_cyc_int:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.ret_reg:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.pc[8]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.pc[7]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.pc[6]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.pc[5]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.pc[4]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.pc[3]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.pc[2]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.pc[1]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.pc[0]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[7]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[6]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[5]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[4]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[3]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[2]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[1]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[0]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.stack_ptr[3]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.stack_ptr[2]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.stack_ptr[1]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.stack_ptr[0]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.pc[9]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.addr_jmp_reg[9]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.addr_jmp_reg[8]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.addr_jmp_reg[7]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.addr_jmp_reg[6]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.addr_jmp_reg[5]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.addr_jmp_reg[4]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.addr_jmp_reg[3]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.addr_jmp_reg[2]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.addr_jmp_reg[1]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.addr_jmp_reg[0]:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.carry_flag_int:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.br_enb_reg:C Not Done
lm8_inst.u1_isp8.u1_isp8_flow_cntl.zero_flag:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.delta:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.sample_d2:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.sample_d1:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.accum_rdy:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.rollover:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.count[2]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.count[1]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.count[0]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.raw_data_d1[2]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.raw_data_d1[1]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.raw_data_d1[0]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.accum[10]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.accum[9]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.accum[8]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.accum[7]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.accum[6]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.accum[5]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.accum[4]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.accum[3]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.accum[2]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.accum[1]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.accum[0]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.raw_data_d1[7]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.raw_data_d1[6]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.raw_data_d1[5]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.raw_data_d1[4]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.raw_data_d1[3]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.counter[9:0]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.sigma[9:0]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.ave_data_out[7]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.ave_data_out[6]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.ave_data_out[5]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.ave_data_out[4]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.ave_data_out[3]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.ave_data_out[2]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.ave_data_out[1]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.box_ave.ave_data_out[0]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.accum[7]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.accum[6]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.accum[5]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.accum[4]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.accum[3]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.accum[2]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.accum[1]:C Not Done
adc_wb_inst.adc_inst.SSD_ADC.accum[0]:C Not Done
SD_CORE_i0.CMD_PHY_i0.cmd_shift_n:C Not Done
SD_CORE_i0.CMD_PHY_i0.cmd_shift:C Not Done
SD_CORE_i0.DATA_PHY_i0.fifo2host:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_tx_done:C Not Done
SD_CORE_i0.DATA_PHY_i0.fifo_empty:C Not Done
SD_CORE_i0.DATA_PHY_i0.card_bit_sel_tx:C Not Done
SD_CORE_i0.DATA_PHY_i0.sd_bit_sel_tx:C Not Done
SD_CORE_i0.DATA_PHY_i0.host2fifo:C Not Done
SD_CORE_i0.DATA_PHY_i0.fifo_q[7]:C Not Done
SD_CORE_i0.DATA_PHY_i0.fifo_q[6]:C Not Done
SD_CORE_i0.DATA_PHY_i0.fifo_q[5]:C Not Done
SD_CORE_i0.DATA_PHY_i0.fifo_q[4]:C Not Done
SD_CORE_i0.DATA_PHY_i0.fifo_q[3]:C Not Done
SD_CORE_i0.DATA_PHY_i0.fifo_q[2]:C Not Done
SD_CORE_i0.DATA_PHY_i0.fifo_q[1]:C Not Done
SD_CORE_i0.DATA_PHY_i0.fifo_q[0]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_count[4:0]:C Not Done
SD_CORE_i0.init_clk[5:0]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i0.CRC[15]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i0.CRC[14]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i0.CRC[13]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i0.CRC[12]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i0.CRC[11]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i0.CRC[10]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i0.CRC[9]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i0.CRC[8]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i0.CRC[7]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i0.CRC[6]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i0.CRC[5]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i0.CRC[4]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i0.CRC[3]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i0.CRC[2]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i0.CRC[1]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i0.CRC[0]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i1.CRC[15]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i1.CRC[14]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i1.CRC[13]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i1.CRC[12]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i1.CRC[11]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i1.CRC[10]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i1.CRC[9]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i1.CRC[8]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i1.CRC[7]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i1.CRC[6]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i1.CRC[5]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i1.CRC[4]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i1.CRC[3]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i1.CRC[2]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i1.CRC[1]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i1.CRC[0]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i2.CRC[15]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i2.CRC[14]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i2.CRC[13]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i2.CRC[12]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i2.CRC[11]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i2.CRC[10]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i2.CRC[9]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i2.CRC[8]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i2.CRC[7]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i2.CRC[6]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i2.CRC[5]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i2.CRC[4]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i2.CRC[3]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i2.CRC[2]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i2.CRC[1]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i2.CRC[0]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i3.CRC[15]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i3.CRC[14]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i3.CRC[13]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i3.CRC[12]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i3.CRC[11]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i3.CRC[10]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i3.CRC[9]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i3.CRC[8]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i3.CRC[7]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i3.CRC[6]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i3.CRC[5]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i3.CRC[4]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i3.CRC[3]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i3.CRC[2]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i3.CRC[1]:C Not Done
SD_CORE_i0.DATA_PHY_i0.CRC16_i3.CRC[0]:C Not Done
SD_CORE_i0.DATA_PHY_i0.fifo_f_flag_1:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d0_shift[15]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d0_shift[14]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d0_shift[13]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d0_shift[12]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d0_shift[11]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d0_shift[10]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d0_shift[9]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d0_shift[8]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d0_shift[7]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d0_shift[6]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d0_shift[5]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d0_shift[4]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d0_shift[3]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d0_shift[2]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d0_shift[1]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d0_shift[0]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d1_shift[15]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d1_shift[14]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d1_shift[13]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d1_shift[12]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d1_shift[11]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d1_shift[10]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d1_shift[9]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d1_shift[8]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d1_shift[7]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d1_shift[6]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d1_shift[5]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d1_shift[4]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d1_shift[3]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d1_shift[2]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d1_shift[1]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d1_shift[0]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d2_shift[15]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d2_shift[14]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d2_shift[13]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d2_shift[12]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d2_shift[11]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d2_shift[10]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d2_shift[9]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d2_shift[8]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d2_shift[7]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d2_shift[6]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d2_shift[5]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d2_shift[4]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d2_shift[3]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d2_shift[2]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d2_shift[1]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d2_shift[0]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d3_shift[15]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d3_shift[14]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d3_shift[13]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d3_shift[12]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d3_shift[11]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d3_shift[10]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d3_shift[9]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d3_shift[8]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d3_shift[7]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d3_shift[6]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d3_shift[5]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d3_shift[4]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d3_shift[3]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d3_shift[2]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d3_shift[1]:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_d3_shift[0]:C Not Done
SD_CORE_i0.DATA_PHY_i0.pause_crc16_load:C Not Done
SD_CORE_i0.DATA_PHY_i0.crc16_load[0]:C Not Done
SD_CORE_i0.DATA_PHY_i0.res_shift:C Not Done
SD_CORE_i0.control_wb_r[1]:C Not Done
SD_CORE_i0.control_wb_r[0]:C Not Done
SD_CORE_i0.cmd_0_wb_r[5]:C Not Done
SD_CORE_i0.cmd_0_wb_r[4]:C Not Done
SD_CORE_i0.cmd_0_wb_r[3]:C Not Done
SD_CORE_i0.cmd_0_wb_r[2]:C Not Done
SD_CORE_i0.cmd_0_wb_r[1]:C Not Done
SD_CORE_i0.cmd_0_wb_r[0]:C Not Done
SD_CORE_i0.cmd_1_wb_r[7]:C Not Done
SD_CORE_i0.cmd_1_wb_r[6]:C Not Done
SD_CORE_i0.cmd_1_wb_r[5]:C Not Done
SD_CORE_i0.cmd_1_wb_r[4]:C Not Done
SD_CORE_i0.cmd_1_wb_r[3]:C Not Done
SD_CORE_i0.cmd_1_wb_r[2]:C Not Done
SD_CORE_i0.cmd_1_wb_r[1]:C Not Done
SD_CORE_i0.cmd_1_wb_r[0]:C Not Done
SD_CORE_i0.cmd_2_wb_r[7]:C Not Done
SD_CORE_i0.cmd_2_wb_r[6]:C Not Done
SD_CORE_i0.cmd_2_wb_r[5]:C Not Done
SD_CORE_i0.cmd_2_wb_r[4]:C Not Done
SD_CORE_i0.cmd_2_wb_r[3]:C Not Done
SD_CORE_i0.cmd_2_wb_r[2]:C Not Done
SD_CORE_i0.cmd_2_wb_r[1]:C Not Done
SD_CORE_i0.cmd_2_wb_r[0]:C Not Done
SD_CORE_i0.cmd_3_wb_r[7]:C Not Done
SD_CORE_i0.cmd_3_wb_r[6]:C Not Done
SD_CORE_i0.cmd_3_wb_r[5]:C Not Done
SD_CORE_i0.cmd_3_wb_r[4]:C Not Done
SD_CORE_i0.cmd_3_wb_r[3]:C Not Done
SD_CORE_i0.cmd_3_wb_r[2]:C Not Done
SD_CORE_i0.cmd_3_wb_r[1]:C Not Done
SD_CORE_i0.cmd_3_wb_r[0]:C Not Done
SD_CORE_i0.cmd_4_wb_r[7]:C Not Done
SD_CORE_i0.cmd_4_wb_r[6]:C Not Done
SD_CORE_i0.cmd_4_wb_r[5]:C Not Done
SD_CORE_i0.cmd_4_wb_r[4]:C Not Done
SD_CORE_i0.cmd_4_wb_r[3]:C Not Done
SD_CORE_i0.cmd_4_wb_r[2]:C Not Done
SD_CORE_i0.cmd_4_wb_r[1]:C Not Done
SD_CORE_i0.cmd_4_wb_r[0]:C Not Done
##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################]
Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:03s; Memory used current: 89MB peak: 93MB)
Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:03s; Memory used current: 89MB peak: 93MB)
Starting Early Timing Optimization (Time elapsed 0h:00m:04s; Memory used current: 89MB peak: 93MB)
Finished Early Timing Optimization (Time elapsed 0h:00m:06s; Memory used current: 90MB peak: 93MB)
Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:06s; Memory used current: 89MB peak: 93MB)
Finished preparing to map (Time elapsed 0h:00m:07s; Memory used current: 90MB peak: 93MB)
Finished technology mapping (Time elapsed 0h:00m:08s; Memory used current: 101MB peak: 103MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:08s -2.95ns 1139 / 961
2 0h:00m:08s -2.95ns 1137 / 961
------------------------------------------------------------
Timing driven replication report
@N: FX271 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":151:0:151:5|Instance "SD_CORE_i0.DATA_PHY_i0.fifo_f_flag_1" with 78 loads has been replicated 1 time(s) to improve timing
@N: FX271 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":358:0:358:5|Instance "SD_CORE_i0.DATA_PHY_i0.crc16_load[0]" with 69 loads has been replicated 2 time(s) to improve timing
@N: FX271 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":358:0:358:5|Instance "SD_CORE_i0.DATA_PHY_i0.pause_crc16_load" with 4 loads has been replicated 1 time(s) to improve timing
@N: FX271 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":328:6:328:11|Instance "lm8_inst.u1_isp8.genblk11\.genblk12\.page_ptr2[6]" with 40 loads has been replicated 2 time(s) to improve timing
@N: FX271 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":151:0:151:5|Instance "SD_CORE_i0.DATA_PHY_i0.fifo_f_flag_1" with 70 loads has been replicated 3 time(s) to improve timing
@N: FX271 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_io_cntl.v":113:0:113:5|Instance "lm8_inst.u1_isp8.u1_isp8_io_cntl.ext_addr[2]" with 71 loads has been replicated 3 time(s) to improve timing
@N: FX271 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_io_cntl.v":113:0:113:5|Instance "lm8_inst.u1_isp8.u1_isp8_io_cntl.ext_addr[4]" with 33 loads has been replicated 3 time(s) to improve timing
@N: FX271 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_io_cntl.v":113:0:113:5|Instance "lm8_inst.u1_isp8.u1_isp8_io_cntl.ext_addr[1]" with 91 loads has been replicated 3 time(s) to improve timing
@N: FX271 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_io_cntl.v":113:0:113:5|Instance "lm8_inst.u1_isp8.u1_isp8_io_cntl.ext_addr[0]" with 80 loads has been replicated 3 time(s) to improve timing
@N: FX271 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":328:6:328:11|Instance "lm8_inst.u1_isp8.g0_6" with 3 loads has been replicated 1 time(s) to improve timing
Added 21 Registers via timing driven replication
Added 15 LUTs via timing driven replication
@N: FX271 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\sd_core.v":124:0:124:5|Instance "SD_CORE_i0.cmd_0_wb_r[0]" with 5 loads has been replicated 1 time(s) to improve timing
@N: FX271 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\sd_core.v":124:0:124:5|Instance "SD_CORE_i0.cmd_0_wb_r[2]" with 4 loads has been replicated 1 time(s) to improve timing
@N: FX271 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\sd_core.v":124:0:124:5|Instance "SD_CORE_i0.cmd_0_wb_r[5]" with 4 loads has been replicated 1 time(s) to improve timing
@N: FX271 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\sd_core.v":124:0:124:5|Instance "SD_CORE_i0.cmd_0_wb_r[3]" with 5 loads has been replicated 1 time(s) to improve timing
@N: FX271 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\sd_core.v":124:0:124:5|Instance "SD_CORE_i0.cmd_0_wb_r[4]" with 5 loads has been replicated 1 time(s) to improve timing
@N: FX271 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\sd_core.v":124:0:124:5|Instance "SD_CORE_i0.cmd_0_wb_r[1]" with 5 loads has been replicated 1 time(s) to improve timing
@N: FX271 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1044\source\spi_wb.v":342:3:342:8|Instance "SPI_INST.genblk19\.genblk20\.c_status[1]" with 26 loads has been replicated 2 time(s) to improve timing
@N: FX271 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\rd1044\source\spi_wb.v":342:3:342:8|Instance "SPI_INST.genblk19\.genblk20\.c_status[0]" with 24 loads has been replicated 2 time(s) to improve timing
@N: FX271 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":328:6:328:11|Instance "lm8_inst.u1_isp8.din_rd_0_i[4]" with 3 loads has been replicated 1 time(s) to improve timing
@N: FX271 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":328:6:328:11|Instance "lm8_inst.u1_isp8.din_rd_0_i[6]" with 5 loads has been replicated 3 time(s) to improve timing
@N: FX271 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":316:6:316:11|Instance "lm8_inst.u1_isp8.din_rd_0_i[1]" with 3 loads has been replicated 1 time(s) to improve timing
Added 10 Registers via timing driven replication
Added 5 LUTs via timing driven replication
@N: FX271 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\reset_gen.v":74:0:74:5|Instance "reset_gen_inst.rst1_out" with 490 loads has been replicated 1 time(s) to improve timing
@N: FX271 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_io_cntl.v":113:0:113:5|Instance "lm8_inst.u1_isp8.u1_isp8_io_cntl.ext_addr[3]" with 18 loads has been replicated 2 time(s) to improve timing
@N: FX271 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\cmd_phy.v":320:0:320:5|Instance "SD_CORE_i0.CMD_PHY_i0.res_shift" with 146 loads has been replicated 3 time(s) to improve timing
@N: FX271 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\reset_gen.v":74:0:74:5|Instance "reset_gen_inst.rst1_out" with 70 loads has been replicated 3 time(s) to improve timing
Added 9 Registers via timing driven replication
Added 2 LUTs via timing driven replication
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:11s -2.01ns 1179 / 1001
2 0h:00m:11s -2.01ns 1179 / 1001
3 0h:00m:11s -2.01ns 1179 / 1001
4 0h:00m:11s -2.01ns 1179 / 1001
------------------------------------------------------------
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:11s -2.01ns 1179 / 1001
2 0h:00m:11s -2.01ns 1179 / 1001
3 0h:00m:11s -2.01ns 1179 / 1001
4 0h:00m:11s -2.01ns 1179 / 1001
------------------------------------------------------------
Net buffering Report for view:work.xo_mini_soc_demo(verilog):
No nets needed buffering.
@N: MF322 |Retiming summary: 1 registers retimed to 1
##### BEGIN RETIMING REPORT #####
Retiming summary : 1 registers retimed to 1
Original and Pipelined registers replaced by retiming :
clk_div_0
New registers created by retiming :
clk_div_ret_3
##### END RETIMING REPORT #####
Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:12s; Memory used current: 102MB peak: 103MB)
@N: FX164 |The option to pack flops in the IOB has not been specified
@N: FX623 |Packing into LUT62
@A: BN291 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\wave_read.v":70:1:70:6|Boundary register WAVE_PROCESSOR.PWM_reg.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\wave_read.v":70:1:70:6|Boundary register WAVE_PROCESSOR.cnt_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\wave_read.v":70:1:70:6|Boundary register WAVE_PROCESSOR.cnt_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\wave_read.v":70:1:70:6|Boundary register WAVE_PROCESSOR.cnt_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\wave_read.v":70:1:70:6|Boundary register WAVE_PROCESSOR.cnt_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\wave_read.v":70:1:70:6|Boundary register WAVE_PROCESSOR.cnt_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\wave_read.v":70:1:70:6|Boundary register WAVE_PROCESSOR.cnt_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\wave_read.v":70:1:70:6|Boundary register WAVE_PROCESSOR.cnt_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\wave_read.v":70:1:70:6|Boundary register WAVE_PROCESSOR.cnt_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
Warning: Found 12 combinational loops!
@W: BN137 :|Found combinational loop during mapping at net I_189.t1
1) instance work.xo_mini_soc_demo(verilog)-I_189.lat, output net "I_189.t1" in work.xo_mini_soc_demo(verilog)
net I_189.t1
input pin I_189.lat/B[0]
instance I_189.lat (cell mux)
output pin I_189.lat/OUT[0]
net I_189.t1
@W: BN137 :|Found combinational loop during mapping at net I_190.t1
2) instance work.xo_mini_soc_demo(verilog)-I_190.lat, output net "I_190.t1" in work.xo_mini_soc_demo(verilog)
net I_190.t1
input pin I_190.lat/B[0]
instance I_190.lat (cell mux)
output pin I_190.lat/OUT[0]
net I_190.t1
@W: BN137 :|Found combinational loop during mapping at net I_191.t1
3) instance work.xo_mini_soc_demo(verilog)-I_191.lat, output net "I_191.t1" in work.xo_mini_soc_demo(verilog)
net I_191.t1
input pin I_191.lat/B[0]
instance I_191.lat (cell mux)
output pin I_191.lat/OUT[0]
net I_191.t1
@W: BN137 :|Found combinational loop during mapping at net I_192.t1
4) instance work.xo_mini_soc_demo(verilog)-I_192.lat, output net "I_192.t1" in work.xo_mini_soc_demo(verilog)
net I_192.t1
input pin I_192.lat/B[0]
instance I_192.lat (cell mux)
output pin I_192.lat/OUT[0]
net I_192.t1
@W: BN137 :|Found combinational loop during mapping at net I_193.t1
5) instance work.xo_mini_soc_demo(verilog)-I_193.lat, output net "I_193.t1" in work.xo_mini_soc_demo(verilog)
net I_193.t1
input pin I_193.lat/B[0]
instance I_193.lat (cell mux)
output pin I_193.lat/OUT[0]
net I_193.t1
@W: BN137 :|Found combinational loop during mapping at net I_194.t1
6) instance work.xo_mini_soc_demo(verilog)-I_194.lat, output net "I_194.t1" in work.xo_mini_soc_demo(verilog)
net I_194.t1
input pin I_194.lat/B[0]
instance I_194.lat (cell mux)
output pin I_194.lat/OUT[0]
net I_194.t1
@W: BN137 :|Found combinational loop during mapping at net I_195.t1
7) instance work.xo_mini_soc_demo(verilog)-I_195.lat, output net "I_195.t1" in work.xo_mini_soc_demo(verilog)
net I_195.t1
input pin I_195.lat/B[0]
instance I_195.lat (cell mux)
output pin I_195.lat/OUT[0]
net I_195.t1
@W: BN137 :|Found combinational loop during mapping at net I_188.t1
8) instance work.xo_mini_soc_demo(verilog)-I_188.lat, output net "I_188.t1" in work.xo_mini_soc_demo(verilog)
net I_188.t1
input pin I_188.lat/B[0]
instance I_188.lat (cell mux)
output pin I_188.lat/OUT[0]
net I_188.t1
@W: BN137 :|Found combinational loop during mapping at net I_199.t1
9) instance work.xo_mini_soc_demo(verilog)-I_199.lat, output net "I_199.t1" in work.xo_mini_soc_demo(verilog)
net I_199.t1
input pin I_199.lat/A[0]
instance I_199.lat (cell mux)
output pin I_199.lat/OUT[0]
net I_199.t1
@W: BN137 :|Found combinational loop during mapping at net I_198.t1
10) instance work.xo_mini_soc_demo(verilog)-I_198.lat, output net "I_198.t1" in work.xo_mini_soc_demo(verilog)
net I_198.t1
input pin I_198.lat/A[0]
instance I_198.lat (cell mux)
output pin I_198.lat/OUT[0]
net I_198.t1
@W: BN137 :|Found combinational loop during mapping at net I_197.t1
11) instance work.xo_mini_soc_demo(verilog)-I_197.lat, output net "I_197.t1" in work.xo_mini_soc_demo(verilog)
net I_197.t1
input pin I_197.lat/A[0]
instance I_197.lat (cell mux)
output pin I_197.lat/OUT[0]
net I_197.t1
@W: BN137 :|Found combinational loop during mapping at net I_196.t1
12) instance work.xo_mini_soc_demo(verilog)-I_196.lat, output net "I_196.t1" in work.xo_mini_soc_demo(verilog)
net I_196.t1
input pin I_196.lat/A[0]
instance I_196.lat (cell mux)
output pin I_196.lat/OUT[0]
net I_196.t1
End of loops
@W: MT420 |Found inferred clock xo_mini_soc_demo|xin with period 5.00ns. A user-defined clock should be declared on object "p:xin"
@W: MT420 |Found inferred clock audio_clk_gen_62500000s_16000s_7s|clkout_inferred_clock with period 5.00ns. A user-defined clock should be declared on object "n:AUDIO_CLK_GEN_INST.clkout"
@W: MT420 |Found inferred clock xo_mini_soc_demo|clk_div_inferred_clock with period 5.00ns. A user-defined clock should be declared on object "n:clk_div"
@W: MT246 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\sd\data_phy.v":200:9:200:19|Blackbox pmi_fifo is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_alu.v":110:15:110:24|Blackbox pmi_addsub_8s_8s_off_XO2_pmi_addsub is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_flow_cntl.v":354:28:354:41|Blackbox pmi_distributed_spram_16s_4s_12s_noreg_none_binary_XO2_pmi_distributed_spram_Z1 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":306:15:306:26|Blackbox pmi_rom_1024s_10s_18s_noreg_disable_async_prom_init\.hex_hex_XO2_pmi_rom_Z2 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\latticemico8_v3_0_verilog\source\isp8_core.v":372:33:372:45|Blackbox pmi_distributed_dpram_32s_5s_8s_noreg_none_binary_XO2_pmi_distributed_dpram_Z4 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\lm8_top.v":130:21:130:33|Blackbox pmi_distributed_spram_32s_5s_8s_noreg_none_binary_XO2_pmi_distributed_spram_Z5 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\rom_ebr_wb.v":68:12:68:23|Blackbox pmi_rom_1024s_10s_8s_noreg_disable_sync_menu\.hex_hex_XO_pmi_rom_Z9 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"c:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\source\audio_buffer.v":40:5:40:13|Blackbox pmi_fifo_dc_Z10 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
##### START OF TIMING REPORT #####[
# Timing Report written on Mon Oct 04 16:26:44 2010
#
Top view: xo_mini_soc_demo
Requested Frequency: 200.0 MHz
Wire load mode: top
Paths requested: 3
Constraint File(s):
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..
Performance Summary
*******************
Worst slack in design: -3.288
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
---------------------------------------------------------------------------------------------------------------------------------------------------------------
audio_clk_gen_62500000s_16000s_7s|clkout_inferred_clock 200.0 MHz 295.2 MHz 5.000 3.387 1.613 inferred Inferred_clkgroup_2
xo_mini_soc_demo|clk_div_inferred_clock 200.0 MHz 86.4 MHz 5.000 11.576 -3.288 inferred Inferred_clkgroup_1
xo_mini_soc_demo|xin 200.0 MHz 438.0 MHz 5.000 2.283 2.717 inferred Inferred_clkgroup_0
System 200.0 MHz 177.6 MHz 5.000 5.632 -0.632 system default_clkgroup
===============================================================================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
xo_mini_soc_demo|xin xo_mini_soc_demo|xin | 5.000 2.717 | No paths - | No paths - | No paths -
xo_mini_soc_demo|clk_div_inferred_clock xo_mini_soc_demo|clk_div_inferred_clock | 5.000 -1.555 | 5.000 -0.360 | 2.500 -1.883 | 2.500 -3.288
audio_clk_gen_62500000s_16000s_7s|clkout_inferred_clock audio_clk_gen_62500000s_16000s_7s|clkout_inferred_clock | 5.000 1.613 | No paths - | No paths - | No paths -
============================================================================================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
Input Ports:
Port Starting User Arrival Required
Name Reference Constraint Time Time Slack
Clock
----------------------------------------------------------------------------------
analog_cmp_n NA NA NA NA NA
analog_cmp_p System (rising) NA 0.000 3.153
rst_n NA NA NA NA NA
scl System (rising) NA 0.000 3.820
sd_cmd System (rising) NA 0.000 2.979
sd_data[0] System (rising) NA 0.000 2.164
sd_data[1] System (rising) NA 0.000 2.164
sd_data[2] System (rising) NA 0.000 2.164
sd_data[3] System (rising) NA 0.000 2.164
sda System (rising) NA 0.000 3.820
spi_miso System (rising) NA 0.000 3.153
sw[0] System (rising) NA 0.000 0.343
sw[1] System (rising) NA 0.000 0.444
sw[2] System (rising) NA 0.000 0.529
sw[3] System (rising) NA 0.000 0.529
uart_rx System (rising) NA 0.000 3.153
xin System (rising) NA 0.000 -0.632
==================================================================================
Output Ports:
Port Starting User Arrival Required
Name Reference Constraint Time Time Slack
Clock
---------------------------------------------------------------------------------------------------------------------
analog_out xo_mini_soc_demo|clk_div_inferred_clock (rising) NA 4.272 5.000
audio_pwm_out System (rising) NA 4.187 5.000
led[0] xo_mini_soc_demo|clk_div_inferred_clock (rising) NA 4.187 5.000
led[1] xo_mini_soc_demo|clk_div_inferred_clock (rising) NA 4.187 5.000
led[2] xo_mini_soc_demo|clk_div_inferred_clock (rising) NA 4.187 5.000
led[3] xo_mini_soc_demo|clk_div_inferred_clock (rising) NA 4.187 5.000
scl xo_mini_soc_demo|clk_div_inferred_clock (rising) NA 4.234 5.000
sd_clk NA NA NA NA NA
sd_clk2 NA NA NA NA NA
sd_cmd xo_mini_soc_demo|clk_div_inferred_clock (falling) NA 5.240 5.000
sd_data[0] xo_mini_soc_demo|clk_div_inferred_clock (rising) NA 7.345 5.000
sd_data[1] xo_mini_soc_demo|clk_div_inferred_clock (rising) NA 7.345 5.000
sd_data[2] xo_mini_soc_demo|clk_div_inferred_clock (rising) NA 7.345 5.000
sd_data[3] xo_mini_soc_demo|clk_div_inferred_clock (rising) NA 7.345 5.000
sda xo_mini_soc_demo|clk_div_inferred_clock (rising) NA 4.234 5.000
spi_csn xo_mini_soc_demo|clk_div_inferred_clock (rising) NA 4.187 5.000
spi_mosi xo_mini_soc_demo|clk_div_inferred_clock (rising) NA 4.187 5.000
spi_sclk xo_mini_soc_demo|clk_div_inferred_clock (rising) NA 4.328 5.000
uart_tx xo_mini_soc_demo|clk_div_inferred_clock (rising) NA 5.071 5.000
xout NA NA NA NA NA
=====================================================================================================================
##### END OF TIMING REPORT #####]
---------------------------------------
Resource Usage Report
Part: lfxp2_8e-5
Register bits: 1000 of 8352 (12%)
Latch bits: 4
PIC Latch: 4
I/O cells: 29
Details:
BB: 7
CCU2B: 93
FD1P3AX: 106
FD1P3BX: 17
FD1P3DX: 572
FD1P3IX: 12
FD1P3JX: 1
FD1S3AX: 41
FD1S3BX: 16
FD1S3DX: 189
FD1S3IX: 32
FD1S3JX: 2
GSR: 1
IB: 8
IFS1P3DX: 3
IFS1P3JX: 2
IFS1S1B: 4
ILVDS: 1
INV: 21
L6MUX21: 20
OB: 13
OFS1P3BX: 1
OFS1P3DX: 6
ORCALUT4: 1176
PFUMX: 51
PUR: 1
VHI: 1
VLO: 1
fanbuf: 1
Finished restoring hierarchy (Time elapsed 0h:00m:13s; Memory used current: 103MB peak: 104MB)
Writing Analyst data base C:\lattice\projects\xo2_cntrl_brd\b - tp rev1\references\xo_control\machxo_control_dev_kit\demo_machxo_control_soc\project\xo_mini_soc_demo.srm
@N: MF203 |Set autoconstraint_io
Finished Writing Netlist Databases (Time elapsed 0h:00m:14s; Memory used current: 99MB peak: 104MB)
Writing EDIF Netlist and constraint files
D-2010.03L-SP1
Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:14s; Memory used current: 103MB peak: 105MB)
Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:14s; Memory used current: 101MB peak: 105MB)
================= Gated clock report =================
The following instances have NOT been converted
Seq Inst Instance Port Clock Reason for not converting
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
SD_CORE_i0.CMD_PHY_i0.CRC7_CMD_I0.CRC[6] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.CRC7_CMD_I0.CRC[5] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.CRC7_CMD_I0.CRC[4] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.CRC7_CMD_I0.CRC[3] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.CRC7_CMD_I0.CRC[2] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.CRC7_CMD_I0.CRC[1] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.CRC7_CMD_I0.CRC[0] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.CRC7_RES_I0.CRC[6] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.CRC7_RES_I0.CRC[5] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.CRC7_RES_I0.CRC[4] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.CRC7_RES_I0.CRC[3] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.CRC7_RES_I0.CRC[2] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.CRC7_RES_I0.CRC[1] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.CRC7_RES_I0.CRC[0] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[47] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[46] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[45] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[44] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[43] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[42] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[41] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[40] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[39] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[38] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[37] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[36] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[35] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[34] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[33] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[32] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[31] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[30] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[29] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[28] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[27] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[26] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[25] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[24] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[23] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[22] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[21] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[20] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[19] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[18] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[17] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[16] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[15] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[14] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[13] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[12] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[11] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[10] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[9] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[8] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[7] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[6] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd_cc[5] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[5] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd_cc[4] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[4] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[3] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd_cc[3] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[2] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd_cc[2] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd_cc[1] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd_load[1] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[1] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd[0] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd_cc[0] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd_load[0] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd_shift CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd_shift_n CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd_tristate CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.cmd_tx CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.crc7_done CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.crc7_done_b CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[135] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[134] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[133] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[132] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[131] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[130] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[129] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[128] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[127] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[126] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[125] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[124] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[123] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[122] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[121] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[120] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[119] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[118] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[117] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[116] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[115] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[114] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[113] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[112] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[111] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[110] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[109] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[108] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[107] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[106] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[105] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[104] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[103] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[102] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[101] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[100] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[99] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[98] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[97] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[96] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[95] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[94] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[93] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[92] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[91] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[90] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[89] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[88] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[87] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[86] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[85] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[84] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[83] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[82] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[81] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[80] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[79] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[78] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[77] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[76] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[75] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[74] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[73] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[72] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[71] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[70] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[69] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[68] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[67] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[66] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[65] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[64] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[63] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[62] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[61] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[60] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[59] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[58] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[57] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[56] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[55] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[54] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[53] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[52] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[51] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[50] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[49] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[48] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[47] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[46] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[45] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[44] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[43] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[42] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[41] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[40] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[39] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[38] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[37] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[36] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[35] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[34] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[33] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[32] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[31] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[30] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[29] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[28] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[27] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[26] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[25] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[24] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[23] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[22] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[21] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[20] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[19] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[18] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[17] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[16] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[15] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[14] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[13] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[12] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[11] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[10] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[9] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[8] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res_c[7] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[7] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res_c[6] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[6] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res_c[5] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[5] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[4] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res_c[4] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[3] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res_c[3] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res_c[2] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[2] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res_c[1] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res[1] CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res_c[0] CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res_crc7_en CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res_done CK SD_CORE_i0.CMD_PHY_i0.CN Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res_shift CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res_shift_fast CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res_shift_rep1 CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0.CMD_PHY_i0.res_shift_rep2 CK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
SD_CORE_i0_CMD_PHY_i0_resio[0] SCLK SD_CORE_i0.cmd_clk_i Gated clock does not have declared clock, add/enable clock constraint in SDC file.
==============================================================================================================================================================================
================= End gated clock report =================
Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:14s; Memory used current: 101MB peak: 105MB)
Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:14s; Memory used current: 101MB peak: 105MB)
@N: MF333 |Generated clock conversion enabled, but no generated clocks found in design
Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:14s; Memory used current: 101MB peak: 105MB)
Warning: Found 12 combinational loops!
@W: BN137 :|Found combinational loop during mapping at net I_196.t1
1) instance work.xo_mini_soc_demo(verilog)-I_196.lat, output net "I_196.t1" in work.xo_mini_soc_demo(verilog)
net I_196.t1
input pin I_196.lat/B
instance I_196.lat (cell ORCALUT4)
output pin I_196.lat/Z
net I_196.t1
@W: BN137 :|Found combinational loop during mapping at net I_197.t1
2) instance work.xo_mini_soc_demo(verilog)-I_197.lat, output net "I_197.t1" in work.xo_mini_soc_demo(verilog)
net I_197.t1
input pin I_197.lat/B
instance I_197.lat (cell ORCALUT4)
output pin I_197.lat/Z
net I_197.t1
@W: BN137 :|Found combinational loop during mapping at net I_198.t1
3) instance work.xo_mini_soc_demo(verilog)-I_198.lat, output net "I_198.t1" in work.xo_mini_soc_demo(verilog)
net I_198.t1
input pin I_198.lat/B
instance I_198.lat (cell ORCALUT4)
output pin I_198.lat/Z
net I_198.t1
@W: BN137 :|Found combinational loop during mapping at net I_199.t1
4) instance work.xo_mini_soc_demo(verilog)-I_199.lat, output net "I_199.t1" in work.xo_mini_soc_demo(verilog)
net I_199.t1
input pin I_199.lat/A
instance I_199.lat (cell ORCALUT4)
output pin I_199.lat/Z
net I_199.t1
@W: BN137 :|Found combinational loop during mapping at net I_191.t1
5) instance work.xo_mini_soc_demo(verilog)-I_191.lat, output net "I_191.t1" in work.xo_mini_soc_demo(verilog)
net I_191.t1
input pin I_191.lat/B
instance I_191.lat (cell ORCALUT4)
output pin I_191.lat/Z
net I_191.t1
@W: BN137 :|Found combinational loop during mapping at net I_189.t1
6) instance work.xo_mini_soc_demo(verilog)-I_189.lat, output net "I_189.t1" in work.xo_mini_soc_demo(verilog)
net I_189.t1
input pin I_189.lat/B
instance I_189.lat (cell ORCALUT4)
output pin I_189.lat/Z
net I_189.t1
@W: BN137 :|Found combinational loop during mapping at net I_192.t1
7) instance work.xo_mini_soc_demo(verilog)-I_192.lat, output net "I_192.t1" in work.xo_mini_soc_demo(verilog)
net I_192.t1
input pin I_192.lat/B
instance I_192.lat (cell ORCALUT4)
output pin I_192.lat/Z
net I_192.t1
@W: BN137 :|Found combinational loop during mapping at net I_188.t1
8) instance work.xo_mini_soc_demo(verilog)-I_188.lat, output net "I_188.t1" in work.xo_mini_soc_demo(verilog)
net I_188.t1
input pin I_188.lat/B
instance I_188.lat (cell ORCALUT4)
output pin I_188.lat/Z
net I_188.t1
@W: BN137 :|Found combinational loop during mapping at net I_195.t1
9) instance work.xo_mini_soc_demo(verilog)-I_195.lat, output net "I_195.t1" in work.xo_mini_soc_demo(verilog)
net I_195.t1
input pin I_195.lat/B
instance I_195.lat (cell ORCALUT4)
output pin I_195.lat/Z
net I_195.t1
@W: BN137 :|Found combinational loop during mapping at net I_194.t1
10) instance work.xo_mini_soc_demo(verilog)-I_194.lat, output net "I_194.t1" in work.xo_mini_soc_demo(verilog)
net I_194.t1
input pin I_194.lat/B
instance I_194.lat (cell ORCALUT4)
output pin I_194.lat/Z
net I_194.t1
@W: BN137 :|Found combinational loop during mapping at net I_190.t1
11) instance work.xo_mini_soc_demo(verilog)-I_190.lat, output net "I_190.t1" in work.xo_mini_soc_demo(verilog)
net I_190.t1
input pin I_190.lat/B
instance I_190.lat (cell ORCALUT4)
output pin I_190.lat/Z
net I_190.t1
@W: BN137 :|Found combinational loop during mapping at net I_193.t1
12) instance work.xo_mini_soc_demo(verilog)-I_193.lat, output net "I_193.t1" in work.xo_mini_soc_demo(verilog)
net I_193.t1
input pin I_193.lat/B
instance I_193.lat (cell ORCALUT4)
output pin I_193.lat/Z
net I_193.t1
End of loops
##### START OF TIMING REPORT #####[
# Timing Report written on Mon Oct 04 16:26:47 2010
#
Top view: xo_mini_soc_demo
Requested Frequency: 200.0 MHz
Wire load mode: top
Paths requested: 3
Constraint File(s):
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..
Performance Summary
*******************
Worst slack in design: -3.300
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
---------------------------------------------------------------------------------------------------------------------------------------------------------------
audio_clk_gen_62500000s_16000s_7s|clkout_inferred_clock 200.0 MHz 295.2 MHz 5.000 3.387 1.613 inferred Inferred_clkgroup_2
xo_mini_soc_demo|clk_div_inferred_clock 200.0 MHz 86.2 MHz 5.000 11.600 -3.300 inferred Inferred_clkgroup_1
xo_mini_soc_demo|xin 200.0 MHz 438.0 MHz 5.000 2.283 2.717 inferred Inferred_clkgroup_0
System 200.0 MHz 177.6 MHz 5.000 5.632 -0.632 system default_clkgroup
===============================================================================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
xo_mini_soc_demo|xin xo_mini_soc_demo|xin | 5.000 2.717 | No paths - | No paths - | No paths -
xo_mini_soc_demo|clk_div_inferred_clock xo_mini_soc_demo|clk_div_inferred_clock | 5.000 -1.555 | 5.000 -0.360 | 2.500 -1.883 | 2.500 -3.300
audio_clk_gen_62500000s_16000s_7s|clkout_inferred_clock audio_clk_gen_62500000s_16000s_7s|clkout_inferred_clock | 5.000 1.613 | No paths - | No paths - | No paths -
============================================================================================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
Input Ports:
Port Starting User Arrival Required
Name Reference Constraint Time Time Slack
Clock
----------------------------------------------------------------------------------
analog_cmp_n NA NA NA NA NA
analog_cmp_p System (rising) NA 0.000 3.153
rst_n NA NA NA NA NA
scl System (rising) NA 0.000 3.820
sd_cmd System (rising) NA 0.000 2.979
sd_data[0] System (rising) NA 0.000 2.164
sd_data[1] System (rising) NA 0.000 2.164
sd_data[2] System (rising) NA 0.000 2.164
sd_data[3] System (rising) NA 0.000 2.164
sda System (rising) NA 0.000 3.820
spi_miso System (rising) NA 0.000 3.153
sw[0] System (rising) NA 0.000 0.343
sw[1] System (rising) NA 0.000 0.444
sw[2] System (rising) NA 0.000 0.529
sw[3] System (rising) NA 0.000 0.529
uart_rx System (rising) NA 0.000 3.153
xin System (rising) NA 0.000 -0.632
==================================================================================
Output Ports:
Port Starting User Arrival Required
Name Reference Constraint Time Time Slack
Clock
---------------------------------------------------------------------------------------------------------------------
analog_out xo_mini_soc_demo|clk_div_inferred_clock (rising) NA 4.272 5.000
audio_pwm_out System (rising) NA 4.187 5.000
led[0] xo_mini_soc_demo|clk_div_inferred_clock (rising) NA 4.187 5.000
led[1] xo_mini_soc_demo|clk_div_inferred_clock (rising) NA 4.187 5.000
led[2] xo_mini_soc_demo|clk_div_inferred_clock (rising) NA 4.187 5.000
led[3] xo_mini_soc_demo|clk_div_inferred_clock (rising) NA 4.187 5.000
scl xo_mini_soc_demo|clk_div_inferred_clock (rising) NA 4.234 5.000
sd_clk NA NA NA NA NA
sd_clk2 NA NA NA NA NA
sd_cmd xo_mini_soc_demo|clk_div_inferred_clock (falling) NA 5.240 5.000
sd_data[0] xo_mini_soc_demo|clk_div_inferred_clock (rising) NA 7.345 5.000
sd_data[1] xo_mini_soc_demo|clk_div_inferred_clock (rising) NA 7.345 5.000
sd_data[2] xo_mini_soc_demo|clk_div_inferred_clock (rising) NA 7.345 5.000
sd_data[3] xo_mini_soc_demo|clk_div_inferred_clock (rising) NA 7.345 5.000
sda xo_mini_soc_demo|clk_div_inferred_clock (rising) NA 4.234 5.000
spi_csn xo_mini_soc_demo|clk_div_inferred_clock (rising) NA 4.187 5.000
spi_mosi xo_mini_soc_demo|clk_div_inferred_clock (rising) NA 4.187 5.000
spi_sclk xo_mini_soc_demo|clk_div_inferred_clock (rising) NA 4.328 5.000
uart_tx xo_mini_soc_demo|clk_div_inferred_clock (rising) NA 5.071 5.000
xout NA NA NA NA NA
=====================================================================================================================
##### END OF TIMING REPORT #####]
Mapper successful!
Process took 0h:00m:19s realtime, 0h:00m:14s cputime
# Mon Oct 04 16:26:47 2010
###########################################################]
Generated from the file 'C:\LATTICE\Projects\XO2_CNTRL_BRD\b - tp rev1\references\xo_control\MachXO_Control_Dev_Kit\Demo_MachXO_Control_SoC\project\xo_mini_soc_demo.srf'