#-- Synopsys, Inc.
#-- Version D-2010.03L-SP1
#-- Project file C:\documents and settings\cwest\desktop\machxo2_pico_demos\soc\demo_machxo2_control_soc3\demo_machxo2_control_soc\project\run_options.txt
#-- Written on Sun Dec 26 16:56:19 2010


#project files
add_file -verilog "C:/ispTOOLS/ispcpld/../cae_library/synthesis/verilog/machxo2.v"
add_file -verilog "./control_SoC_demo.h"
add_file -verilog "../source/audio_buffer.v"
add_file -verilog "../source/clk_gen.v"
add_file -verilog "../source/wave_read.v"
add_file -verilog "../source/pwm.v"
add_file -verilog "../source/LCDEncoding4to1.v"
add_file -verilog "../source/lcdencoding4to1com.v"
add_file -verilog "../source/IPexpress/EFB_Module.v"
add_file -verilog "../source/uptime_wb.v"
add_file -verilog "../rd1046/source/i2c_master_registers.v"
add_file -verilog "../rd1046/source/i2c_master_bit_ctrl.v"
add_file -verilog "../rd1046/source/i2c_master_byte_ctrl.v"
add_file -verilog "../rd1046/source/i2c_master_wb_top.v"
add_file -verilog "../rd1044/Source/Spi_wb.v"
add_file -verilog "../latticemico8_v3_1_verilog/source/isp8_core.v"
add_file -verilog "../source/rom_ebr_wb.v"
add_file -verilog "../source/IPexpress/PLL.v"
add_file -verilog "../source/pll_soft_wb.v"
add_file -verilog "../rd1066/source/verilog/box_ave.v"
add_file -verilog "../rd1066/source/verilog/sigmadelta_adc.v"
add_file -verilog "../rd1066/source/verilog/adc_top.v"
add_file -verilog "../source/adc_wb.v"
add_file -verilog "../rd1042/source/modem.v"
add_file -verilog "../rd1042/source/uart_core.v"
add_file -verilog "../source/lm8_top.v"
add_file -verilog "../latticemico8_v3_1_verilog/source/isp8_io_cntl.v"
add_file -verilog "../latticemico8_v3_1_verilog/source/isp8_flow_cntl.v"
add_file -verilog "../latticemico8_v3_1_verilog/source/isp8_alu.v"
add_file -verilog "../latticemico8_v3_1_verilog/source/isp8_idec.v"
add_file -verilog "../rd1043/source/lm8_wb.v"
add_file -verilog "../source/led_sw_wb.v"
add_file -verilog "../source/reset_gen.v"
add_file -verilog "../source/control_soc_demo.v"


#implementation: "project"
impl -add project -type fpga

#
#implementation attributes

set_option -vlog_std v2001
set_option -num_critical_paths 3
set_option -num_startend_points 0

#device options
set_option -technology MACHXO2
set_option -part LCMXO2_1200HC
set_option -package TG100C
set_option -speed_grade -5
set_option -part_companion ""

#compilation/mapping options
set_option -top_module "control_soc_demo"

# mapper_options
set_option -frequency 1
set_option -auto_constrain_io 1
set_option -write_verilog 0
set_option -write_vhdl 0

# Lattice XP
set_option -maxfan 100
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -pipe 0
set_option -forcegsr false
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3
set_option -update_models_cp 0

# NFilter
set_option -popfeed 0
set_option -constprop 0
set_option -createhierarchy 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 1
set_option -resource_sharing 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 0

#set result format/file last
project -result_file "./control_soc_demo.edi"

#set log file 
set_option log_file "C:/documents and settings/cwest/desktop/machxo2_pico_demos/soc/demo_machxo2_control_soc3/demo_machxo2_control_soc/project/control_soc_demo.srf" 
impl -active "project"
