@W: MO111 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\intface.v":110:12:110:25|Tristate driver fifo_empty_thr on net fifo_empty_thr has its enable tied to GND (module intface_Z7) 
@W: MO111 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\rxcver.v":97:27:97:42|Tristate driver fifo_almost_full on net fifo_almost_full has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO) 
@W: MO111 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\rxcver.v":96:27:96:36|Tristate driver fifo_empty on net fifo_empty has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO) 
@W: MO111 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\rxcver.v":89:26:89:33|Tristate driver rbr_fifo_1 on net rbr_fifo_1 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO) 
@W: MO111 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\rxcver.v":89:26:89:33|Tristate driver rbr_fifo_2 on net rbr_fifo_2 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO) 
@W: MO111 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\rxcver.v":89:26:89:33|Tristate driver rbr_fifo_3 on net rbr_fifo_3 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO) 
@W: MO111 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\rxcver.v":89:26:89:33|Tristate driver rbr_fifo_4 on net rbr_fifo_4 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO) 
@W: MO111 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\rxcver.v":89:26:89:33|Tristate driver rbr_fifo_5 on net rbr_fifo_5 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO) 
@W: MO111 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\rxcver.v":89:26:89:33|Tristate driver rbr_fifo_6 on net rbr_fifo_6 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO) 
@W: MO111 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\rxcver.v":89:26:89:33|Tristate driver rbr_fifo_7 on net rbr_fifo_7 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO) 
@W: MO111 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\rxcver.v":89:26:89:33|Tristate driver rbr_fifo_8 on net rbr_fifo_8 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO) 
@W: MO111 :|Tristate driver fifo_empty_thr_t on net fifo_empty_thr has its enable tied to GND (module uart_core_12000s_115200s_3s_8s_0s) 
@W: MO111 :|Tristate driver RBR_FIFO_t[0] on net RBR_FIFO[0] has its enable tied to GND (module uart_core_12000s_115200s_3s_8s_0s) 
@W: MO111 :|Tristate driver RBR_FIFO_t[1] on net RBR_FIFO[1] has its enable tied to GND (module uart_core_12000s_115200s_3s_8s_0s) 
@W: MO111 :|Tristate driver RBR_FIFO_t[2] on net RBR_FIFO[2] has its enable tied to GND (module uart_core_12000s_115200s_3s_8s_0s) 
@W: MO111 :|Tristate driver RBR_FIFO_t[3] on net RBR_FIFO[3] has its enable tied to GND (module uart_core_12000s_115200s_3s_8s_0s) 
@W: MO111 :|Tristate driver RBR_FIFO_t[4] on net RBR_FIFO[4] has its enable tied to GND (module uart_core_12000s_115200s_3s_8s_0s) 
@W: MO111 :|Tristate driver RBR_FIFO_t[5] on net RBR_FIFO[5] has its enable tied to GND (module uart_core_12000s_115200s_3s_8s_0s) 
@W: MO111 :|Tristate driver RBR_FIFO_t[6] on net RBR_FIFO[6] has its enable tied to GND (module uart_core_12000s_115200s_3s_8s_0s) 
@W: MO111 :|Tristate driver RBR_FIFO_t[7] on net RBR_FIFO[7] has its enable tied to GND (module uart_core_12000s_115200s_3s_8s_0s) 
@W: MO111 :|Tristate driver fifo_empty_t on net fifo_empty has its enable tied to GND (module uart_core_12000s_115200s_3s_8s_0s) 
@W: MO111 :|Tristate driver fifo_almost_full_t on net fifo_almost_full has its enable tied to GND (module uart_core_12000s_115200s_3s_8s_0s) 
@W: MO111 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\environment_scanning.v":97:18:97:21|Tristate driver I2CAlert on net I2CAlert has its enable tied to GND (module Environment_Scanning) 
@W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\modem.v":99:2:99:7|Removing sequential instance UART_INST.u_modem.dsrn_d1,  because it is equivalent to instance UART_INST.u_modem.dcdn_d1
@W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\modem.v":99:2:99:7|Removing sequential instance UART_INST.u_modem.dcdn_d1,  because it is equivalent to instance UART_INST.u_modem.ctsn_d1
@W: BN137 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\environment_scanning.v":266:21:266:36|Found combinational loop during mapping at net DebounceRingOSCb[16]
@W: BN241 |Unable to finish printing loop, loop close not found
@W: BN137 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\ringosc.v":58:21:58:28|Found combinational loop during mapping at net clkselect_wb_inst.RingOSC_inst.RingOSCb[6]
@W: BN241 |Unable to finish printing loop, loop close not found
@W: MT462 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\environment_scanning.v":800:33:800:73|Net DebounceRingOSCb_1[1] appears to be an unidentified clock source. Assuming default frequency. 
@W: MT462 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\environment_scanning.v":823:26:823:55|Net ToggleUSERSTDBY appears to be an unidentified clock source. Assuming default frequency. 
@W: MT462 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\ringosc.v":63:25:63:50|Net clkselect_wb_inst.RingOSC_inst.RingOSCb_1[1] appears to be an unidentified clock source. Assuming default frequency. 
@W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\modem.v":99:2:99:7|Removing instance UART_INST.u_modem.msr_reg[1],  because it is equivalent to instance UART_INST.u_modem.msr_reg[0]
@W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\modem.v":99:2:99:7|Removing instance UART_INST.u_modem.msr_reg[3],  because it is equivalent to instance UART_INST.u_modem.msr_reg[0]
@W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\modem.v":99:2:99:7|Removing instance UART_INST.u_modem.msr_reg[7],  because it is equivalent to instance UART_INST.u_modem.msr_reg[6]
@W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\modem.v":99:2:99:7|Removing instance UART_INST.u_modem.msr_reg[6],  because it is equivalent to instance UART_INST.u_modem.msr_reg[5]
@W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\modem.v":99:2:99:7|Removing instance UART_INST.u_modem.msr_reg[5],  because it is equivalent to instance UART_INST.u_modem.msr_reg[4]
@W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\intface.v":225:3:225:8|Removing instance UART_INST.u_intface.divisor[15],  because it is equivalent to instance UART_INST.u_intface.divisor[14]
@W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\intface.v":225:3:225:8|Removing instance UART_INST.u_intface.divisor[14],  because it is equivalent to instance UART_INST.u_intface.divisor[13]
@W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\intface.v":225:3:225:8|Removing instance UART_INST.u_intface.divisor[13],  because it is equivalent to instance UART_INST.u_intface.divisor[12]
@W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\intface.v":225:3:225:8|Removing instance UART_INST.u_intface.divisor[12],  because it is equivalent to instance UART_INST.u_intface.divisor[11]
@W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\intface.v":225:3:225:8|Removing instance UART_INST.u_intface.divisor[11],  because it is equivalent to instance UART_INST.u_intface.divisor[10]
@W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\intface.v":225:3:225:8|Removing instance UART_INST.u_intface.divisor[9],  because it is equivalent to instance UART_INST.u_intface.divisor[10]
@W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\intface.v":225:3:225:8|Removing instance UART_INST.u_intface.divisor[8],  because it is equivalent to instance UART_INST.u_intface.divisor[10]
@W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_flow_cntl.v":209:3:209:8|Removing instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[0],  because it is equivalent to instance lm8_inst.u1_isp8.din_rd1[0]
@W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_flow_cntl.v":209:3:209:8|Removing instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[1],  because it is equivalent to instance lm8_inst.u1_isp8.din_rd1[1]
@W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_flow_cntl.v":209:3:209:8|Removing instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[2],  because it is equivalent to instance lm8_inst.u1_isp8.din_rd1[2]
@W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_flow_cntl.v":209:3:209:8|Removing instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[3],  because it is equivalent to instance lm8_inst.u1_isp8.din_rd1[3]
@W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_flow_cntl.v":209:3:209:8|Removing instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[4],  because it is equivalent to instance lm8_inst.u1_isp8.din_rd1[4]
@W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_flow_cntl.v":209:3:209:8|Removing instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[5],  because it is equivalent to instance lm8_inst.u1_isp8.din_rd1[5]
@W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_flow_cntl.v":209:3:209:8|Removing instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[6],  because it is equivalent to instance lm8_inst.u1_isp8.din_rd1[6]
@W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_flow_cntl.v":209:3:209:8|Removing instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[7],  because it is equivalent to instance lm8_inst.u1_isp8.din_rd1[7]
@W: MO111 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\environment_scanning.v":81:8:81:15|Tristate driver I2CAlert_obuft.un1[0] on net I2CAlert has its enable tied to GND (module Environment_Scanning) 
@W: MO129 :|Sequential instance DebounceRingOSCen.res_reg_0 reduced to a combinational gate by constant propagation
@W: BN137 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\environment_scanning.v":266:21:266:36|Found combinational loop during mapping at net DebounceRingOSCb[16]
@W: BN241 |Unable to finish printing loop, loop close not found
@W: BN137 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\ringosc.v":58:21:58:28|Found combinational loop during mapping at net clkselect_wb_inst.RingOSC_inst.RingOSCb[6]
@W: BN241 |Unable to finish printing loop, loop close not found
@W: MT246 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\source\powercntr.v":23:10:23:20|Blackbox PCNTR is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\source\ipexpress\efb_module.v":111:8:111:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\rom_ebr_wb.v":68:12:68:23|Blackbox pmi_rom_1024s_10s_8s_noreg_disable_sync_menu\.hex_hex_XO2_pmi_rom_Z8 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\lm8_top.v":130:21:130:33|Blackbox pmi_distributed_spram_32s_5s_8s_noreg_none_binary_XO2_pmi_distributed_spram_Z5 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_core.v":434:33:434:45|Blackbox pmi_distributed_dpram_32s_5s_8s_noreg_none_binary_XO2_pmi_distributed_dpram_Z4 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_core.v":320:15:320:26|Blackbox pmi_rom_2048s_11s_18s_noreg_disable_async_prom_init\.hex_hex_XO2_pmi_rom_Z2 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_flow_cntl.v":394:30:394:43|Blackbox pmi_distributed_spram_16s_4s_13s_noreg_none_binary_XO2_pmi_distributed_spram_Z1 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_alu.v":95:18:95:27|Blackbox pmi_addsub_8s_8s_off_XO2_pmi_addsub is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\clksource_wb.v":127:6:127:14|Blackbox OSCH is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\source\ipexpress\bankcontroller.v":13:11:13:16|Blackbox BCINRD is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock Environment_Scanning|clk_USB with period 1000.00ns. Please declare a user-defined clock on object "p:clk_USB"
@W: MT420 |Found inferred clock clkselect_wb|oscclk_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:clkselect_wb_inst.oscclk"
