Place & Route TRACE Report
Loading design for application trce from file environment_scanning_impl1.ncd.
Design name: Environment_Scanning
NCD version: 3.2
Vendor: LATTICE
Device: LCMXO2-1200ZE
Package: CSBGA132
Performance: 3
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/Diamond/diamond/2.0/ispfpga.
Package Status: Final Version 1.33
Performance Hardware Data Status: Final Version 22.4
Setup and Hold Report
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Lattice TRACE Report - Setup, Version Diamond Version 2.0.0.154
Tue Jul 24 16:23:41 2012
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2012 Lattice Semiconductor Corporation, All rights reserved.
Report Information
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Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o Environment_Scanning_impl1.twr Environment_Scanning_impl1.ncd Environment_Scanning_impl1.prf
Design file: environment_scanning_impl1.ncd
Preference file: environment_scanning_impl1.prf
Device,speed: LCMXO2-1200ZE,3
Report level: verbose report, limited to 10 items per preference
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Preference Summary
FREQUENCY NET "clk" 2.000000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
Report: 16.479MHz is the maximum frequency for this preference.
FREQUENCY NET "clkselect_wb_inst/oscclk" 2.080000 MHz (0 errors) 20 items scored, 0 timing errors detected.
Report: 14.858MHz is the maximum frequency for this preference.
5 potential circuit loops found in timing analysis.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
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================================================================================
Preference: FREQUENCY NET "clk" 2.000000 MHz ;
4096 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 439.317ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q clkselect_wb_inst/oscclkclean_inst/CalbrateRingOSC (from clkselect_wb_inst/RingOSCraw_c +)
Destination: FF Data in clkselect_wb_inst/OSCEnbDelay[0] (to clk +)
Delay: 7.193ns (21.9% logic, 78.1% route), 2 logic levels.
Constraint Details:
7.193ns physical path delay clkselect_wb_inst/oscclkclean_inst/SLICE_470 to clkselect_wb_inst/SLICE_159 meets
500.000ns delay constraint less
53.023ns skew and
0.467ns CE_SET requirement (totaling 446.510ns) by 439.317ns
Physical Path Details:
Data path clkselect_wb_inst/oscclkclean_inst/SLICE_470 to clkselect_wb_inst/SLICE_159:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.801 R3C3C.CLK to R3C3C.Q0 clkselect_wb_inst/oscclkclean_inst/SLICE_470 (from clkselect_wb_inst/RingOSCraw_c)
ROUTE 21 3.669 R3C3C.Q0 to R4C4C.B0 clkselect_wb_inst/CalbrateRingOSC
CTOF_DEL --- 0.774 R4C4C.B0 to R4C4C.F0 clkselect_wb_inst/SLICE_666
ROUTE 3 1.949 R4C4C.F0 to R4C2A.CE clkselect_wb_inst/OSCEnbDelaye (to clk)
--------
7.193 (21.9% logic, 78.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_470:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.440 OSC.OSC to R3C2D.CLK clkselect_wb_inst/oscclk
REG_DEL --- 0.801 R3C2D.CLK to R3C2D.Q0 clkselect_wb_inst/SLICE_144
ROUTE 2 5.056 R3C2D.Q0 to R4C21D.B1 clkselect_wb_inst/clk_switch_inst1/transfer2
CTOF_DEL --- 0.774 R4C21D.B1 to R4C21D.F1 SLICE_527
ROUTE 289 5.766 R4C21D.F1 to R8C5B.CLK clk
REG_DEL --- 0.801 R8C5B.CLK to R8C5B.Q0 SLICE_340
ROUTE 1 4.265 R8C5B.Q0 to R7C10A.B1 TimeOutStandby
CTOF_DEL --- 0.774 R7C10A.B1 to R7C10A.F1 SLICE_506
ROUTE 1 1.771 R7C10A.F1 to R7C12C.CLK ToggleUSERSTDBY_i
REG_DEL --- 0.801 R7C12C.CLK to R7C12C.Q0 SLICE_417
ROUTE 18 4.788 R7C12C.Q0 to *NTR.USERSTDBY USERSTDBY
STDBY_DEL --- 14.150 *NTR.USERSTDBY to PCNTR.STDBY PowerCntr_inst/PCNTR_Inst0
ROUTE 15 3.757 PCNTR.STDBY to R2C3D.A1 STDBY
CTOF_DEL --- 0.774 R2C3D.A1 to R2C3D.F1 clkselect_wb_inst/RingOSC_inst/SLICE_661
ROUTE 1 0.830 R2C3D.F1 to R2C3D.C0 clkselect_wb_inst/RingOSC_inst/RingOSCb[1]
CTOF_DEL --- 0.774 R2C3D.C0 to R2C3D.F0 clkselect_wb_inst/RingOSC_inst/SLICE_661
ROUTE 1 0.631 R2C3D.F0 to R2C3C.D0 clkselect_wb_inst/RingOSC_inst/RingOSCb[2]
CTOF_DEL --- 0.774 R2C3C.D0 to R2C3C.F0 clkselect_wb_inst/RingOSC_inst/SLICE_662
ROUTE 1 0.830 R2C3C.F0 to R2C3C.C1 clkselect_wb_inst/RingOSC_inst/RingOSCb[3]
CTOF_DEL --- 0.774 R2C3C.C1 to R2C3C.F1 clkselect_wb_inst/RingOSC_inst/SLICE_662
ROUTE 1 1.304 R2C3C.F1 to R2C3B.B0 clkselect_wb_inst/RingOSC_inst/RingOSCb[4]
CTOF_DEL --- 0.774 R2C3B.B0 to R2C3B.F0 clkselect_wb_inst/RingOSC_inst/SLICE_663
ROUTE 2 0.871 R2C3B.F0 to R2C3B.C1 clkselect_wb_inst/RingOSC_inst/RingOSCb[5]
CTOF_DEL --- 0.774 R2C3B.C1 to R2C3B.F1 clkselect_wb_inst/RingOSC_inst/SLICE_663
ROUTE 20 7.008 R2C3B.F1 to R3C3C.CLK clkselect_wb_inst/RingOSCraw_c
--------
67.062 (33.9% logic, 66.1% route), 12 logic levels.
Destination Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/SLICE_159:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.499 OSC.OSC to R4C21D.D1 clkselect_wb_inst/oscclk
CTOF_DEL --- 0.774 R4C21D.D1 to R4C21D.F1 SLICE_527
ROUTE 289 5.766 R4C21D.F1 to R4C2A.CLK clk
--------
14.039 (5.5% logic, 94.5% route), 1 logic levels.
Passed: The following path meets requirements by 439.317ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q clkselect_wb_inst/oscclkclean_inst/CalbrateRingOSC (from clkselect_wb_inst/RingOSCraw_c +)
Destination: FF Data in clkselect_wb_inst/OSCEnbDelay[2] (to clk +)
FF clkselect_wb_inst/OSCEnbDelay[1]
Delay: 7.193ns (21.9% logic, 78.1% route), 2 logic levels.
Constraint Details:
7.193ns physical path delay clkselect_wb_inst/oscclkclean_inst/SLICE_470 to clkselect_wb_inst/SLICE_158 meets
500.000ns delay constraint less
53.023ns skew and
0.467ns CE_SET requirement (totaling 446.510ns) by 439.317ns
Physical Path Details:
Data path clkselect_wb_inst/oscclkclean_inst/SLICE_470 to clkselect_wb_inst/SLICE_158:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.801 R3C3C.CLK to R3C3C.Q0 clkselect_wb_inst/oscclkclean_inst/SLICE_470 (from clkselect_wb_inst/RingOSCraw_c)
ROUTE 21 3.669 R3C3C.Q0 to R4C4C.B0 clkselect_wb_inst/CalbrateRingOSC
CTOF_DEL --- 0.774 R4C4C.B0 to R4C4C.F0 clkselect_wb_inst/SLICE_666
ROUTE 3 1.949 R4C4C.F0 to R4C2B.CE clkselect_wb_inst/OSCEnbDelaye (to clk)
--------
7.193 (21.9% logic, 78.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_470:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.440 OSC.OSC to R3C2D.CLK clkselect_wb_inst/oscclk
REG_DEL --- 0.801 R3C2D.CLK to R3C2D.Q0 clkselect_wb_inst/SLICE_144
ROUTE 2 5.056 R3C2D.Q0 to R4C21D.B1 clkselect_wb_inst/clk_switch_inst1/transfer2
CTOF_DEL --- 0.774 R4C21D.B1 to R4C21D.F1 SLICE_527
ROUTE 289 5.766 R4C21D.F1 to R8C5B.CLK clk
REG_DEL --- 0.801 R8C5B.CLK to R8C5B.Q0 SLICE_340
ROUTE 1 4.265 R8C5B.Q0 to R7C10A.B1 TimeOutStandby
CTOF_DEL --- 0.774 R7C10A.B1 to R7C10A.F1 SLICE_506
ROUTE 1 1.771 R7C10A.F1 to R7C12C.CLK ToggleUSERSTDBY_i
REG_DEL --- 0.801 R7C12C.CLK to R7C12C.Q0 SLICE_417
ROUTE 18 4.788 R7C12C.Q0 to *NTR.USERSTDBY USERSTDBY
STDBY_DEL --- 14.150 *NTR.USERSTDBY to PCNTR.STDBY PowerCntr_inst/PCNTR_Inst0
ROUTE 15 3.757 PCNTR.STDBY to R2C3D.A1 STDBY
CTOF_DEL --- 0.774 R2C3D.A1 to R2C3D.F1 clkselect_wb_inst/RingOSC_inst/SLICE_661
ROUTE 1 0.830 R2C3D.F1 to R2C3D.C0 clkselect_wb_inst/RingOSC_inst/RingOSCb[1]
CTOF_DEL --- 0.774 R2C3D.C0 to R2C3D.F0 clkselect_wb_inst/RingOSC_inst/SLICE_661
ROUTE 1 0.631 R2C3D.F0 to R2C3C.D0 clkselect_wb_inst/RingOSC_inst/RingOSCb[2]
CTOF_DEL --- 0.774 R2C3C.D0 to R2C3C.F0 clkselect_wb_inst/RingOSC_inst/SLICE_662
ROUTE 1 0.830 R2C3C.F0 to R2C3C.C1 clkselect_wb_inst/RingOSC_inst/RingOSCb[3]
CTOF_DEL --- 0.774 R2C3C.C1 to R2C3C.F1 clkselect_wb_inst/RingOSC_inst/SLICE_662
ROUTE 1 1.304 R2C3C.F1 to R2C3B.B0 clkselect_wb_inst/RingOSC_inst/RingOSCb[4]
CTOF_DEL --- 0.774 R2C3B.B0 to R2C3B.F0 clkselect_wb_inst/RingOSC_inst/SLICE_663
ROUTE 2 0.871 R2C3B.F0 to R2C3B.C1 clkselect_wb_inst/RingOSC_inst/RingOSCb[5]
CTOF_DEL --- 0.774 R2C3B.C1 to R2C3B.F1 clkselect_wb_inst/RingOSC_inst/SLICE_663
ROUTE 20 7.008 R2C3B.F1 to R3C3C.CLK clkselect_wb_inst/RingOSCraw_c
--------
67.062 (33.9% logic, 66.1% route), 12 logic levels.
Destination Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/SLICE_158:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.499 OSC.OSC to R4C21D.D1 clkselect_wb_inst/oscclk
CTOF_DEL --- 0.774 R4C21D.D1 to R4C21D.F1 SLICE_527
ROUTE 289 5.766 R4C21D.F1 to R4C2B.CLK clk
--------
14.039 (5.5% logic, 94.5% route), 1 logic levels.
Passed: The following path meets requirements by 439.317ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q clkselect_wb_inst/oscclkclean_inst/CalbrateRingOSC (from clkselect_wb_inst/RingOSCraw_c +)
Destination: FF Data in clkselect_wb_inst/OSCEnbDelay[4] (to clk +)
FF clkselect_wb_inst/OSCEnbDelay[3]
Delay: 7.193ns (21.9% logic, 78.1% route), 2 logic levels.
Constraint Details:
7.193ns physical path delay clkselect_wb_inst/oscclkclean_inst/SLICE_470 to clkselect_wb_inst/SLICE_157 meets
500.000ns delay constraint less
53.023ns skew and
0.467ns CE_SET requirement (totaling 446.510ns) by 439.317ns
Physical Path Details:
Data path clkselect_wb_inst/oscclkclean_inst/SLICE_470 to clkselect_wb_inst/SLICE_157:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.801 R3C3C.CLK to R3C3C.Q0 clkselect_wb_inst/oscclkclean_inst/SLICE_470 (from clkselect_wb_inst/RingOSCraw_c)
ROUTE 21 3.669 R3C3C.Q0 to R4C4C.B0 clkselect_wb_inst/CalbrateRingOSC
CTOF_DEL --- 0.774 R4C4C.B0 to R4C4C.F0 clkselect_wb_inst/SLICE_666
ROUTE 3 1.949 R4C4C.F0 to R4C2C.CE clkselect_wb_inst/OSCEnbDelaye (to clk)
--------
7.193 (21.9% logic, 78.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_470:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.440 OSC.OSC to R3C2D.CLK clkselect_wb_inst/oscclk
REG_DEL --- 0.801 R3C2D.CLK to R3C2D.Q0 clkselect_wb_inst/SLICE_144
ROUTE 2 5.056 R3C2D.Q0 to R4C21D.B1 clkselect_wb_inst/clk_switch_inst1/transfer2
CTOF_DEL --- 0.774 R4C21D.B1 to R4C21D.F1 SLICE_527
ROUTE 289 5.766 R4C21D.F1 to R8C5B.CLK clk
REG_DEL --- 0.801 R8C5B.CLK to R8C5B.Q0 SLICE_340
ROUTE 1 4.265 R8C5B.Q0 to R7C10A.B1 TimeOutStandby
CTOF_DEL --- 0.774 R7C10A.B1 to R7C10A.F1 SLICE_506
ROUTE 1 1.771 R7C10A.F1 to R7C12C.CLK ToggleUSERSTDBY_i
REG_DEL --- 0.801 R7C12C.CLK to R7C12C.Q0 SLICE_417
ROUTE 18 4.788 R7C12C.Q0 to *NTR.USERSTDBY USERSTDBY
STDBY_DEL --- 14.150 *NTR.USERSTDBY to PCNTR.STDBY PowerCntr_inst/PCNTR_Inst0
ROUTE 15 3.757 PCNTR.STDBY to R2C3D.A1 STDBY
CTOF_DEL --- 0.774 R2C3D.A1 to R2C3D.F1 clkselect_wb_inst/RingOSC_inst/SLICE_661
ROUTE 1 0.830 R2C3D.F1 to R2C3D.C0 clkselect_wb_inst/RingOSC_inst/RingOSCb[1]
CTOF_DEL --- 0.774 R2C3D.C0 to R2C3D.F0 clkselect_wb_inst/RingOSC_inst/SLICE_661
ROUTE 1 0.631 R2C3D.F0 to R2C3C.D0 clkselect_wb_inst/RingOSC_inst/RingOSCb[2]
CTOF_DEL --- 0.774 R2C3C.D0 to R2C3C.F0 clkselect_wb_inst/RingOSC_inst/SLICE_662
ROUTE 1 0.830 R2C3C.F0 to R2C3C.C1 clkselect_wb_inst/RingOSC_inst/RingOSCb[3]
CTOF_DEL --- 0.774 R2C3C.C1 to R2C3C.F1 clkselect_wb_inst/RingOSC_inst/SLICE_662
ROUTE 1 1.304 R2C3C.F1 to R2C3B.B0 clkselect_wb_inst/RingOSC_inst/RingOSCb[4]
CTOF_DEL --- 0.774 R2C3B.B0 to R2C3B.F0 clkselect_wb_inst/RingOSC_inst/SLICE_663
ROUTE 2 0.871 R2C3B.F0 to R2C3B.C1 clkselect_wb_inst/RingOSC_inst/RingOSCb[5]
CTOF_DEL --- 0.774 R2C3B.C1 to R2C3B.F1 clkselect_wb_inst/RingOSC_inst/SLICE_663
ROUTE 20 7.008 R2C3B.F1 to R3C3C.CLK clkselect_wb_inst/RingOSCraw_c
--------
67.062 (33.9% logic, 66.1% route), 12 logic levels.
Destination Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/SLICE_157:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.499 OSC.OSC to R4C21D.D1 clkselect_wb_inst/oscclk
CTOF_DEL --- 0.774 R4C21D.D1 to R4C21D.F1 SLICE_527
ROUTE 289 5.766 R4C21D.F1 to R4C2C.CLK clk
--------
14.039 (5.5% logic, 94.5% route), 1 logic levels.
Passed: The following path meets requirements by 439.960ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q clkselect_wb_inst/oscclkclean_inst/CalbrateRingOSC (from clkselect_wb_inst/RingOSCraw_c +)
Destination: FF Data in clkselect_wb_inst/RingOSCEnbDelay[4] (to clk +)
FF clkselect_wb_inst/RingOSCEnbDelay[3]
Delay: 6.550ns (24.0% logic, 76.0% route), 2 logic levels.
Constraint Details:
6.550ns physical path delay clkselect_wb_inst/oscclkclean_inst/SLICE_470 to clkselect_wb_inst/SLICE_154 meets
500.000ns delay constraint less
53.023ns skew and
0.467ns CE_SET requirement (totaling 446.510ns) by 439.960ns
Physical Path Details:
Data path clkselect_wb_inst/oscclkclean_inst/SLICE_470 to clkselect_wb_inst/SLICE_154:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.801 R3C3C.CLK to R3C3C.Q0 clkselect_wb_inst/oscclkclean_inst/SLICE_470 (from clkselect_wb_inst/RingOSCraw_c)
ROUTE 21 2.795 R3C3C.Q0 to R2C4C.B1 clkselect_wb_inst/CalbrateRingOSC
CTOF_DEL --- 0.774 R2C4C.B1 to R2C4C.F1 clkselect_wb_inst/SLICE_471
ROUTE 3 2.180 R2C4C.F1 to R2C5C.CE clkselect_wb_inst/RingOSCEnbDelaye (to clk)
--------
6.550 (24.0% logic, 76.0% route), 2 logic levels.
Clock Skew Details:
Source Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_470:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.440 OSC.OSC to R3C2D.CLK clkselect_wb_inst/oscclk
REG_DEL --- 0.801 R3C2D.CLK to R3C2D.Q0 clkselect_wb_inst/SLICE_144
ROUTE 2 5.056 R3C2D.Q0 to R4C21D.B1 clkselect_wb_inst/clk_switch_inst1/transfer2
CTOF_DEL --- 0.774 R4C21D.B1 to R4C21D.F1 SLICE_527
ROUTE 289 5.766 R4C21D.F1 to R8C5B.CLK clk
REG_DEL --- 0.801 R8C5B.CLK to R8C5B.Q0 SLICE_340
ROUTE 1 4.265 R8C5B.Q0 to R7C10A.B1 TimeOutStandby
CTOF_DEL --- 0.774 R7C10A.B1 to R7C10A.F1 SLICE_506
ROUTE 1 1.771 R7C10A.F1 to R7C12C.CLK ToggleUSERSTDBY_i
REG_DEL --- 0.801 R7C12C.CLK to R7C12C.Q0 SLICE_417
ROUTE 18 4.788 R7C12C.Q0 to *NTR.USERSTDBY USERSTDBY
STDBY_DEL --- 14.150 *NTR.USERSTDBY to PCNTR.STDBY PowerCntr_inst/PCNTR_Inst0
ROUTE 15 3.757 PCNTR.STDBY to R2C3D.A1 STDBY
CTOF_DEL --- 0.774 R2C3D.A1 to R2C3D.F1 clkselect_wb_inst/RingOSC_inst/SLICE_661
ROUTE 1 0.830 R2C3D.F1 to R2C3D.C0 clkselect_wb_inst/RingOSC_inst/RingOSCb[1]
CTOF_DEL --- 0.774 R2C3D.C0 to R2C3D.F0 clkselect_wb_inst/RingOSC_inst/SLICE_661
ROUTE 1 0.631 R2C3D.F0 to R2C3C.D0 clkselect_wb_inst/RingOSC_inst/RingOSCb[2]
CTOF_DEL --- 0.774 R2C3C.D0 to R2C3C.F0 clkselect_wb_inst/RingOSC_inst/SLICE_662
ROUTE 1 0.830 R2C3C.F0 to R2C3C.C1 clkselect_wb_inst/RingOSC_inst/RingOSCb[3]
CTOF_DEL --- 0.774 R2C3C.C1 to R2C3C.F1 clkselect_wb_inst/RingOSC_inst/SLICE_662
ROUTE 1 1.304 R2C3C.F1 to R2C3B.B0 clkselect_wb_inst/RingOSC_inst/RingOSCb[4]
CTOF_DEL --- 0.774 R2C3B.B0 to R2C3B.F0 clkselect_wb_inst/RingOSC_inst/SLICE_663
ROUTE 2 0.871 R2C3B.F0 to R2C3B.C1 clkselect_wb_inst/RingOSC_inst/RingOSCb[5]
CTOF_DEL --- 0.774 R2C3B.C1 to R2C3B.F1 clkselect_wb_inst/RingOSC_inst/SLICE_663
ROUTE 20 7.008 R2C3B.F1 to R3C3C.CLK clkselect_wb_inst/RingOSCraw_c
--------
67.062 (33.9% logic, 66.1% route), 12 logic levels.
Destination Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/SLICE_154:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.499 OSC.OSC to R4C21D.D1 clkselect_wb_inst/oscclk
CTOF_DEL --- 0.774 R4C21D.D1 to R4C21D.F1 SLICE_527
ROUTE 289 5.766 R4C21D.F1 to R2C5C.CLK clk
--------
14.039 (5.5% logic, 94.5% route), 1 logic levels.
Passed: The following path meets requirements by 439.960ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q clkselect_wb_inst/oscclkclean_inst/CalbrateRingOSC (from clkselect_wb_inst/RingOSCraw_c +)
Destination: FF Data in clkselect_wb_inst/RingOSCEnbDelay[2] (to clk +)
FF clkselect_wb_inst/RingOSCEnbDelay[1]
Delay: 6.550ns (24.0% logic, 76.0% route), 2 logic levels.
Constraint Details:
6.550ns physical path delay clkselect_wb_inst/oscclkclean_inst/SLICE_470 to clkselect_wb_inst/SLICE_155 meets
500.000ns delay constraint less
53.023ns skew and
0.467ns CE_SET requirement (totaling 446.510ns) by 439.960ns
Physical Path Details:
Data path clkselect_wb_inst/oscclkclean_inst/SLICE_470 to clkselect_wb_inst/SLICE_155:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.801 R3C3C.CLK to R3C3C.Q0 clkselect_wb_inst/oscclkclean_inst/SLICE_470 (from clkselect_wb_inst/RingOSCraw_c)
ROUTE 21 2.795 R3C3C.Q0 to R2C4C.B1 clkselect_wb_inst/CalbrateRingOSC
CTOF_DEL --- 0.774 R2C4C.B1 to R2C4C.F1 clkselect_wb_inst/SLICE_471
ROUTE 3 2.180 R2C4C.F1 to R2C5B.CE clkselect_wb_inst/RingOSCEnbDelaye (to clk)
--------
6.550 (24.0% logic, 76.0% route), 2 logic levels.
Clock Skew Details:
Source Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_470:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.440 OSC.OSC to R3C2D.CLK clkselect_wb_inst/oscclk
REG_DEL --- 0.801 R3C2D.CLK to R3C2D.Q0 clkselect_wb_inst/SLICE_144
ROUTE 2 5.056 R3C2D.Q0 to R4C21D.B1 clkselect_wb_inst/clk_switch_inst1/transfer2
CTOF_DEL --- 0.774 R4C21D.B1 to R4C21D.F1 SLICE_527
ROUTE 289 5.766 R4C21D.F1 to R8C5B.CLK clk
REG_DEL --- 0.801 R8C5B.CLK to R8C5B.Q0 SLICE_340
ROUTE 1 4.265 R8C5B.Q0 to R7C10A.B1 TimeOutStandby
CTOF_DEL --- 0.774 R7C10A.B1 to R7C10A.F1 SLICE_506
ROUTE 1 1.771 R7C10A.F1 to R7C12C.CLK ToggleUSERSTDBY_i
REG_DEL --- 0.801 R7C12C.CLK to R7C12C.Q0 SLICE_417
ROUTE 18 4.788 R7C12C.Q0 to *NTR.USERSTDBY USERSTDBY
STDBY_DEL --- 14.150 *NTR.USERSTDBY to PCNTR.STDBY PowerCntr_inst/PCNTR_Inst0
ROUTE 15 3.757 PCNTR.STDBY to R2C3D.A1 STDBY
CTOF_DEL --- 0.774 R2C3D.A1 to R2C3D.F1 clkselect_wb_inst/RingOSC_inst/SLICE_661
ROUTE 1 0.830 R2C3D.F1 to R2C3D.C0 clkselect_wb_inst/RingOSC_inst/RingOSCb[1]
CTOF_DEL --- 0.774 R2C3D.C0 to R2C3D.F0 clkselect_wb_inst/RingOSC_inst/SLICE_661
ROUTE 1 0.631 R2C3D.F0 to R2C3C.D0 clkselect_wb_inst/RingOSC_inst/RingOSCb[2]
CTOF_DEL --- 0.774 R2C3C.D0 to R2C3C.F0 clkselect_wb_inst/RingOSC_inst/SLICE_662
ROUTE 1 0.830 R2C3C.F0 to R2C3C.C1 clkselect_wb_inst/RingOSC_inst/RingOSCb[3]
CTOF_DEL --- 0.774 R2C3C.C1 to R2C3C.F1 clkselect_wb_inst/RingOSC_inst/SLICE_662
ROUTE 1 1.304 R2C3C.F1 to R2C3B.B0 clkselect_wb_inst/RingOSC_inst/RingOSCb[4]
CTOF_DEL --- 0.774 R2C3B.B0 to R2C3B.F0 clkselect_wb_inst/RingOSC_inst/SLICE_663
ROUTE 2 0.871 R2C3B.F0 to R2C3B.C1 clkselect_wb_inst/RingOSC_inst/RingOSCb[5]
CTOF_DEL --- 0.774 R2C3B.C1 to R2C3B.F1 clkselect_wb_inst/RingOSC_inst/SLICE_663
ROUTE 20 7.008 R2C3B.F1 to R3C3C.CLK clkselect_wb_inst/RingOSCraw_c
--------
67.062 (33.9% logic, 66.1% route), 12 logic levels.
Destination Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/SLICE_155:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.499 OSC.OSC to R4C21D.D1 clkselect_wb_inst/oscclk
CTOF_DEL --- 0.774 R4C21D.D1 to R4C21D.F1 SLICE_527
ROUTE 289 5.766 R4C21D.F1 to R2C5B.CLK clk
--------
14.039 (5.5% logic, 94.5% route), 1 logic levels.
Passed: The following path meets requirements by 439.960ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q clkselect_wb_inst/oscclkclean_inst/CalbrateRingOSC (from clkselect_wb_inst/RingOSCraw_c +)
Destination: FF Data in clkselect_wb_inst/RingOSCEnbDelay[0] (to clk +)
Delay: 6.550ns (24.0% logic, 76.0% route), 2 logic levels.
Constraint Details:
6.550ns physical path delay clkselect_wb_inst/oscclkclean_inst/SLICE_470 to clkselect_wb_inst/SLICE_156 meets
500.000ns delay constraint less
53.023ns skew and
0.467ns CE_SET requirement (totaling 446.510ns) by 439.960ns
Physical Path Details:
Data path clkselect_wb_inst/oscclkclean_inst/SLICE_470 to clkselect_wb_inst/SLICE_156:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.801 R3C3C.CLK to R3C3C.Q0 clkselect_wb_inst/oscclkclean_inst/SLICE_470 (from clkselect_wb_inst/RingOSCraw_c)
ROUTE 21 2.795 R3C3C.Q0 to R2C4C.B1 clkselect_wb_inst/CalbrateRingOSC
CTOF_DEL --- 0.774 R2C4C.B1 to R2C4C.F1 clkselect_wb_inst/SLICE_471
ROUTE 3 2.180 R2C4C.F1 to R2C5A.CE clkselect_wb_inst/RingOSCEnbDelaye (to clk)
--------
6.550 (24.0% logic, 76.0% route), 2 logic levels.
Clock Skew Details:
Source Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_470:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.440 OSC.OSC to R3C2D.CLK clkselect_wb_inst/oscclk
REG_DEL --- 0.801 R3C2D.CLK to R3C2D.Q0 clkselect_wb_inst/SLICE_144
ROUTE 2 5.056 R3C2D.Q0 to R4C21D.B1 clkselect_wb_inst/clk_switch_inst1/transfer2
CTOF_DEL --- 0.774 R4C21D.B1 to R4C21D.F1 SLICE_527
ROUTE 289 5.766 R4C21D.F1 to R8C5B.CLK clk
REG_DEL --- 0.801 R8C5B.CLK to R8C5B.Q0 SLICE_340
ROUTE 1 4.265 R8C5B.Q0 to R7C10A.B1 TimeOutStandby
CTOF_DEL --- 0.774 R7C10A.B1 to R7C10A.F1 SLICE_506
ROUTE 1 1.771 R7C10A.F1 to R7C12C.CLK ToggleUSERSTDBY_i
REG_DEL --- 0.801 R7C12C.CLK to R7C12C.Q0 SLICE_417
ROUTE 18 4.788 R7C12C.Q0 to *NTR.USERSTDBY USERSTDBY
STDBY_DEL --- 14.150 *NTR.USERSTDBY to PCNTR.STDBY PowerCntr_inst/PCNTR_Inst0
ROUTE 15 3.757 PCNTR.STDBY to R2C3D.A1 STDBY
CTOF_DEL --- 0.774 R2C3D.A1 to R2C3D.F1 clkselect_wb_inst/RingOSC_inst/SLICE_661
ROUTE 1 0.830 R2C3D.F1 to R2C3D.C0 clkselect_wb_inst/RingOSC_inst/RingOSCb[1]
CTOF_DEL --- 0.774 R2C3D.C0 to R2C3D.F0 clkselect_wb_inst/RingOSC_inst/SLICE_661
ROUTE 1 0.631 R2C3D.F0 to R2C3C.D0 clkselect_wb_inst/RingOSC_inst/RingOSCb[2]
CTOF_DEL --- 0.774 R2C3C.D0 to R2C3C.F0 clkselect_wb_inst/RingOSC_inst/SLICE_662
ROUTE 1 0.830 R2C3C.F0 to R2C3C.C1 clkselect_wb_inst/RingOSC_inst/RingOSCb[3]
CTOF_DEL --- 0.774 R2C3C.C1 to R2C3C.F1 clkselect_wb_inst/RingOSC_inst/SLICE_662
ROUTE 1 1.304 R2C3C.F1 to R2C3B.B0 clkselect_wb_inst/RingOSC_inst/RingOSCb[4]
CTOF_DEL --- 0.774 R2C3B.B0 to R2C3B.F0 clkselect_wb_inst/RingOSC_inst/SLICE_663
ROUTE 2 0.871 R2C3B.F0 to R2C3B.C1 clkselect_wb_inst/RingOSC_inst/RingOSCb[5]
CTOF_DEL --- 0.774 R2C3B.C1 to R2C3B.F1 clkselect_wb_inst/RingOSC_inst/SLICE_663
ROUTE 20 7.008 R2C3B.F1 to R3C3C.CLK clkselect_wb_inst/RingOSCraw_c
--------
67.062 (33.9% logic, 66.1% route), 12 logic levels.
Destination Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/SLICE_156:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.499 OSC.OSC to R4C21D.D1 clkselect_wb_inst/oscclk
CTOF_DEL --- 0.774 R4C21D.D1 to R4C21D.F1 SLICE_527
ROUTE 289 5.766 R4C21D.F1 to R2C5A.CLK clk
--------
14.039 (5.5% logic, 94.5% route), 1 logic levels.
Passed: The following path meets requirements by 458.936ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q USERSTDBY (from ToggleUSERSTDBY_i +)
Destination: FF Data in OscReg4 (to clk +)
FF OscReg3
Delay: 26.442ns (56.5% logic, 43.5% route), 2 logic levels.
Constraint Details:
26.442ns physical path delay SLICE_417 to SLICE_324 meets
500.000ns delay constraint less
13.409ns skew and
1.213ns LSR_SET requirement (totaling 485.378ns) by 458.936ns
Physical Path Details:
Data path SLICE_417 to SLICE_324:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.801 R7C12C.CLK to R7C12C.Q0 SLICE_417 (from ToggleUSERSTDBY_i)
ROUTE 18 4.788 R7C12C.Q0 to *NTR.USERSTDBY USERSTDBY
STDBY_DEL --- 14.150 *NTR.USERSTDBY to PCNTR.STDBY PowerCntr_inst/PCNTR_Inst0
ROUTE 15 6.703 PCNTR.STDBY to R10C20D.LSR STDBY (to clk)
--------
26.442 (56.5% logic, 43.5% route), 2 logic levels.
Clock Skew Details:
Source Clock Path clkselect_wb_inst/OSCH_inst to SLICE_417:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.440 OSC.OSC to R3C2D.CLK clkselect_wb_inst/oscclk
REG_DEL --- 0.801 R3C2D.CLK to R3C2D.Q0 clkselect_wb_inst/SLICE_144
ROUTE 2 5.056 R3C2D.Q0 to R4C21D.B1 clkselect_wb_inst/clk_switch_inst1/transfer2
CTOF_DEL --- 0.774 R4C21D.B1 to R4C21D.F1 SLICE_527
ROUTE 289 5.766 R4C21D.F1 to R8C5B.CLK clk
REG_DEL --- 0.801 R8C5B.CLK to R8C5B.Q0 SLICE_340
ROUTE 1 4.265 R8C5B.Q0 to R7C10A.B1 TimeOutStandby
CTOF_DEL --- 0.774 R7C10A.B1 to R7C10A.F1 SLICE_506
ROUTE 1 1.771 R7C10A.F1 to R7C12C.CLK ToggleUSERSTDBY_i
--------
27.448 (11.5% logic, 88.5% route), 4 logic levels.
Destination Clock Path clkselect_wb_inst/OSCH_inst to SLICE_324:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.499 OSC.OSC to R4C21D.D1 clkselect_wb_inst/oscclk
CTOF_DEL --- 0.774 R4C21D.D1 to R4C21D.F1 SLICE_527
ROUTE 289 5.766 R4C21D.F1 to R10C20D.CLK clk
--------
14.039 (5.5% logic, 94.5% route), 1 logic levels.
Passed: The following path meets requirements by 459.054ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q USERSTDBY (from ToggleUSERSTDBY_i +)
Destination: FF Data in OscReg3_rep0_i_0io (to clk +)
Delay: 27.497ns (54.4% logic, 45.6% route), 2 logic levels.
Constraint Details:
27.497ns physical path delay SLICE_417 to cap_btn3_MGIOL meets
500.000ns delay constraint less
13.182ns skew and
0.267ns LSRREC_SET requirement (totaling 486.551ns) by 459.054ns
Physical Path Details:
Data path SLICE_417 to cap_btn3_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.801 R7C12C.CLK to R7C12C.Q0 SLICE_417 (from ToggleUSERSTDBY_i)
ROUTE 18 4.788 R7C12C.Q0 to *NTR.USERSTDBY USERSTDBY
STDBY_DEL --- 14.150 *NTR.USERSTDBY to PCNTR.STDBY PowerCntr_inst/PCNTR_Inst0
ROUTE 15 7.758 PCNTR.STDBY to IOL_B20A.LSR STDBY (to clk)
--------
27.497 (54.4% logic, 45.6% route), 2 logic levels.
Clock Skew Details:
Source Clock Path clkselect_wb_inst/OSCH_inst to SLICE_417:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.440 OSC.OSC to R3C2D.CLK clkselect_wb_inst/oscclk
REG_DEL --- 0.801 R3C2D.CLK to R3C2D.Q0 clkselect_wb_inst/SLICE_144
ROUTE 2 5.056 R3C2D.Q0 to R4C21D.B1 clkselect_wb_inst/clk_switch_inst1/transfer2
CTOF_DEL --- 0.774 R4C21D.B1 to R4C21D.F1 SLICE_527
ROUTE 289 5.766 R4C21D.F1 to R8C5B.CLK clk
REG_DEL --- 0.801 R8C5B.CLK to R8C5B.Q0 SLICE_340
ROUTE 1 4.265 R8C5B.Q0 to R7C10A.B1 TimeOutStandby
CTOF_DEL --- 0.774 R7C10A.B1 to R7C10A.F1 SLICE_506
ROUTE 1 1.771 R7C10A.F1 to R7C12C.CLK ToggleUSERSTDBY_i
--------
27.448 (11.5% logic, 88.5% route), 4 logic levels.
Destination Clock Path clkselect_wb_inst/OSCH_inst to cap_btn3_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.499 OSC.OSC to R4C21D.D1 clkselect_wb_inst/oscclk
CTOF_DEL --- 0.774 R4C21D.D1 to R4C21D.F1 SLICE_527
ROUTE 289 5.993 R4C21D.F1 to IOL_B20A.CLK clk
--------
14.266 (5.4% logic, 94.6% route), 1 logic levels.
Passed: The following path meets requirements by 459.054ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q USERSTDBY (from ToggleUSERSTDBY_i +)
Destination: FF Data in OscReg4_rep0_i_0io (to clk +)
Delay: 27.497ns (54.4% logic, 45.6% route), 2 logic levels.
Constraint Details:
27.497ns physical path delay SLICE_417 to cap_btn4_MGIOL meets
500.000ns delay constraint less
13.182ns skew and
0.267ns LSRREC_SET requirement (totaling 486.551ns) by 459.054ns
Physical Path Details:
Data path SLICE_417 to cap_btn4_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.801 R7C12C.CLK to R7C12C.Q0 SLICE_417 (from ToggleUSERSTDBY_i)
ROUTE 18 4.788 R7C12C.Q0 to *NTR.USERSTDBY USERSTDBY
STDBY_DEL --- 14.150 *NTR.USERSTDBY to PCNTR.STDBY PowerCntr_inst/PCNTR_Inst0
ROUTE 15 7.758 PCNTR.STDBY to IOL_B20B.LSR STDBY (to clk)
--------
27.497 (54.4% logic, 45.6% route), 2 logic levels.
Clock Skew Details:
Source Clock Path clkselect_wb_inst/OSCH_inst to SLICE_417:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.440 OSC.OSC to R3C2D.CLK clkselect_wb_inst/oscclk
REG_DEL --- 0.801 R3C2D.CLK to R3C2D.Q0 clkselect_wb_inst/SLICE_144
ROUTE 2 5.056 R3C2D.Q0 to R4C21D.B1 clkselect_wb_inst/clk_switch_inst1/transfer2
CTOF_DEL --- 0.774 R4C21D.B1 to R4C21D.F1 SLICE_527
ROUTE 289 5.766 R4C21D.F1 to R8C5B.CLK clk
REG_DEL --- 0.801 R8C5B.CLK to R8C5B.Q0 SLICE_340
ROUTE 1 4.265 R8C5B.Q0 to R7C10A.B1 TimeOutStandby
CTOF_DEL --- 0.774 R7C10A.B1 to R7C10A.F1 SLICE_506
ROUTE 1 1.771 R7C10A.F1 to R7C12C.CLK ToggleUSERSTDBY_i
--------
27.448 (11.5% logic, 88.5% route), 4 logic levels.
Destination Clock Path clkselect_wb_inst/OSCH_inst to cap_btn4_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.499 OSC.OSC to R4C21D.D1 clkselect_wb_inst/oscclk
CTOF_DEL --- 0.774 R4C21D.D1 to R4C21D.F1 SLICE_527
ROUTE 289 5.993 R4C21D.F1 to IOL_B20B.CLK clk
--------
14.266 (5.4% logic, 94.6% route), 1 logic levels.
Passed: The following path meets requirements by 459.779ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q USERSTDBY (from ToggleUSERSTDBY_i +)
Destination: FF Data in OscReg2 (to clk +)
FF OscReg1
Delay: 25.599ns (58.4% logic, 41.6% route), 2 logic levels.
Constraint Details:
25.599ns physical path delay SLICE_417 to SLICE_323 meets
500.000ns delay constraint less
13.409ns skew and
1.213ns LSR_SET requirement (totaling 485.378ns) by 459.779ns
Physical Path Details:
Data path SLICE_417 to SLICE_323:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.801 R7C12C.CLK to R7C12C.Q0 SLICE_417 (from ToggleUSERSTDBY_i)
ROUTE 18 4.788 R7C12C.Q0 to *NTR.USERSTDBY USERSTDBY
STDBY_DEL --- 14.150 *NTR.USERSTDBY to PCNTR.STDBY PowerCntr_inst/PCNTR_Inst0
ROUTE 15 5.860 PCNTR.STDBY to R10C18D.LSR STDBY (to clk)
--------
25.599 (58.4% logic, 41.6% route), 2 logic levels.
Clock Skew Details:
Source Clock Path clkselect_wb_inst/OSCH_inst to SLICE_417:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.440 OSC.OSC to R3C2D.CLK clkselect_wb_inst/oscclk
REG_DEL --- 0.801 R3C2D.CLK to R3C2D.Q0 clkselect_wb_inst/SLICE_144
ROUTE 2 5.056 R3C2D.Q0 to R4C21D.B1 clkselect_wb_inst/clk_switch_inst1/transfer2
CTOF_DEL --- 0.774 R4C21D.B1 to R4C21D.F1 SLICE_527
ROUTE 289 5.766 R4C21D.F1 to R8C5B.CLK clk
REG_DEL --- 0.801 R8C5B.CLK to R8C5B.Q0 SLICE_340
ROUTE 1 4.265 R8C5B.Q0 to R7C10A.B1 TimeOutStandby
CTOF_DEL --- 0.774 R7C10A.B1 to R7C10A.F1 SLICE_506
ROUTE 1 1.771 R7C10A.F1 to R7C12C.CLK ToggleUSERSTDBY_i
--------
27.448 (11.5% logic, 88.5% route), 4 logic levels.
Destination Clock Path clkselect_wb_inst/OSCH_inst to SLICE_323:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.499 OSC.OSC to R4C21D.D1 clkselect_wb_inst/oscclk
CTOF_DEL --- 0.774 R4C21D.D1 to R4C21D.F1 SLICE_527
ROUTE 289 5.766 R4C21D.F1 to R10C18D.CLK clk
--------
14.039 (5.5% logic, 94.5% route), 1 logic levels.
Report: 16.479MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "clkselect_wb_inst/oscclk" 2.080000 MHz ;
20 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 413.467ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q clkselect_wb_inst/oscclkclean_inst/CalbrateRingOSC (from clkselect_wb_inst/RingOSCraw_c +)
Destination: FF Data in clkselect_wb_inst/oscclkclean_inst/RingOSCcnten (to clkselect_wb_inst/oscclk +)
Delay: 7.322ns (32.1% logic, 67.9% route), 3 logic levels.
Constraint Details:
7.322ns physical path delay clkselect_wb_inst/oscclkclean_inst/SLICE_470 to clkselect_wb_inst/oscclkclean_inst/SLICE_481 meets
480.769ns delay constraint less
59.622ns skew and
0.358ns DIN_SET requirement (totaling 420.789ns) by 413.467ns
Physical Path Details:
Data path clkselect_wb_inst/oscclkclean_inst/SLICE_470 to clkselect_wb_inst/oscclkclean_inst/SLICE_481:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.801 R3C3C.CLK to R3C3C.Q0 clkselect_wb_inst/oscclkclean_inst/SLICE_470 (from clkselect_wb_inst/RingOSCraw_c)
ROUTE 21 4.143 R3C3C.Q0 to R8C2B.C1 clkselect_wb_inst/CalbrateRingOSC
CTOF_DEL --- 0.774 R8C2B.C1 to R8C2B.F1 clkselect_wb_inst/oscclkclean_inst/SLICE_481
ROUTE 1 0.830 R8C2B.F1 to R8C2B.C0 clkselect_wb_inst/oscclkclean_inst/RingOSCcnten_0_sqmuxa
CTOF_DEL --- 0.774 R8C2B.C0 to R8C2B.F0 clkselect_wb_inst/oscclkclean_inst/SLICE_481
ROUTE 1 0.000 R8C2B.F0 to R8C2B.DI0 clkselect_wb_inst/oscclkclean_inst/N_4168_0 (to clkselect_wb_inst/oscclk)
--------
7.322 (32.1% logic, 67.9% route), 3 logic levels.
Clock Skew Details:
Source Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_470:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.440 OSC.OSC to R3C2D.CLK clkselect_wb_inst/oscclk
REG_DEL --- 0.801 R3C2D.CLK to R3C2D.Q0 clkselect_wb_inst/SLICE_144
ROUTE 2 5.056 R3C2D.Q0 to R4C21D.B1 clkselect_wb_inst/clk_switch_inst1/transfer2
CTOF_DEL --- 0.774 R4C21D.B1 to R4C21D.F1 SLICE_527
ROUTE 289 5.766 R4C21D.F1 to R8C5B.CLK clk
REG_DEL --- 0.801 R8C5B.CLK to R8C5B.Q0 SLICE_340
ROUTE 1 4.265 R8C5B.Q0 to R7C10A.B1 TimeOutStandby
CTOF_DEL --- 0.774 R7C10A.B1 to R7C10A.F1 SLICE_506
ROUTE 1 1.771 R7C10A.F1 to R7C12C.CLK ToggleUSERSTDBY_i
REG_DEL --- 0.801 R7C12C.CLK to R7C12C.Q0 SLICE_417
ROUTE 18 4.788 R7C12C.Q0 to *NTR.USERSTDBY USERSTDBY
STDBY_DEL --- 14.150 *NTR.USERSTDBY to PCNTR.STDBY PowerCntr_inst/PCNTR_Inst0
ROUTE 15 3.757 PCNTR.STDBY to R2C3D.A1 STDBY
CTOF_DEL --- 0.774 R2C3D.A1 to R2C3D.F1 clkselect_wb_inst/RingOSC_inst/SLICE_661
ROUTE 1 0.830 R2C3D.F1 to R2C3D.C0 clkselect_wb_inst/RingOSC_inst/RingOSCb[1]
CTOF_DEL --- 0.774 R2C3D.C0 to R2C3D.F0 clkselect_wb_inst/RingOSC_inst/SLICE_661
ROUTE 1 0.631 R2C3D.F0 to R2C3C.D0 clkselect_wb_inst/RingOSC_inst/RingOSCb[2]
CTOF_DEL --- 0.774 R2C3C.D0 to R2C3C.F0 clkselect_wb_inst/RingOSC_inst/SLICE_662
ROUTE 1 0.830 R2C3C.F0 to R2C3C.C1 clkselect_wb_inst/RingOSC_inst/RingOSCb[3]
CTOF_DEL --- 0.774 R2C3C.C1 to R2C3C.F1 clkselect_wb_inst/RingOSC_inst/SLICE_662
ROUTE 1 1.304 R2C3C.F1 to R2C3B.B0 clkselect_wb_inst/RingOSC_inst/RingOSCb[4]
CTOF_DEL --- 0.774 R2C3B.B0 to R2C3B.F0 clkselect_wb_inst/RingOSC_inst/SLICE_663
ROUTE 2 0.871 R2C3B.F0 to R2C3B.C1 clkselect_wb_inst/RingOSC_inst/RingOSCb[5]
CTOF_DEL --- 0.774 R2C3B.C1 to R2C3B.F1 clkselect_wb_inst/RingOSC_inst/SLICE_663
ROUTE 20 7.008 R2C3B.F1 to R3C3C.CLK clkselect_wb_inst/RingOSCraw_c
--------
67.062 (33.9% logic, 66.1% route), 12 logic levels.
Destination Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_481:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.440 OSC.OSC to R8C2B.CLK clkselect_wb_inst/oscclk
--------
7.440 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 415.071ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q clkselect_wb_inst/oscclkclean_inst/CalbrateRingOSC (from clkselect_wb_inst/RingOSCraw_c +)
Destination: FF Data in clkselect_wb_inst/oscclkclean_inst/IntOSCcnt[0] (to clkselect_wb_inst/oscclk +)
Delay: 5.718ns (27.5% logic, 72.5% route), 2 logic levels.
Constraint Details:
5.718ns physical path delay clkselect_wb_inst/oscclkclean_inst/SLICE_470 to clkselect_wb_inst/oscclkclean_inst/SLICE_479 meets
480.769ns delay constraint less
59.622ns skew and
0.358ns DIN_SET requirement (totaling 420.789ns) by 415.071ns
Physical Path Details:
Data path clkselect_wb_inst/oscclkclean_inst/SLICE_470 to clkselect_wb_inst/oscclkclean_inst/SLICE_479:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.801 R3C3C.CLK to R3C3C.Q0 clkselect_wb_inst/oscclkclean_inst/SLICE_470 (from clkselect_wb_inst/RingOSCraw_c)
ROUTE 21 4.143 R3C3C.Q0 to R8C2A.C0 clkselect_wb_inst/CalbrateRingOSC
CTOF_DEL --- 0.774 R8C2A.C0 to R8C2A.F0 clkselect_wb_inst/oscclkclean_inst/SLICE_479
ROUTE 1 0.000 R8C2A.F0 to R8C2A.DI0 clkselect_wb_inst/oscclkclean_inst/N_390_i_i (to clkselect_wb_inst/oscclk)
--------
5.718 (27.5% logic, 72.5% route), 2 logic levels.
Clock Skew Details:
Source Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_470:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.440 OSC.OSC to R3C2D.CLK clkselect_wb_inst/oscclk
REG_DEL --- 0.801 R3C2D.CLK to R3C2D.Q0 clkselect_wb_inst/SLICE_144
ROUTE 2 5.056 R3C2D.Q0 to R4C21D.B1 clkselect_wb_inst/clk_switch_inst1/transfer2
CTOF_DEL --- 0.774 R4C21D.B1 to R4C21D.F1 SLICE_527
ROUTE 289 5.766 R4C21D.F1 to R8C5B.CLK clk
REG_DEL --- 0.801 R8C5B.CLK to R8C5B.Q0 SLICE_340
ROUTE 1 4.265 R8C5B.Q0 to R7C10A.B1 TimeOutStandby
CTOF_DEL --- 0.774 R7C10A.B1 to R7C10A.F1 SLICE_506
ROUTE 1 1.771 R7C10A.F1 to R7C12C.CLK ToggleUSERSTDBY_i
REG_DEL --- 0.801 R7C12C.CLK to R7C12C.Q0 SLICE_417
ROUTE 18 4.788 R7C12C.Q0 to *NTR.USERSTDBY USERSTDBY
STDBY_DEL --- 14.150 *NTR.USERSTDBY to PCNTR.STDBY PowerCntr_inst/PCNTR_Inst0
ROUTE 15 3.757 PCNTR.STDBY to R2C3D.A1 STDBY
CTOF_DEL --- 0.774 R2C3D.A1 to R2C3D.F1 clkselect_wb_inst/RingOSC_inst/SLICE_661
ROUTE 1 0.830 R2C3D.F1 to R2C3D.C0 clkselect_wb_inst/RingOSC_inst/RingOSCb[1]
CTOF_DEL --- 0.774 R2C3D.C0 to R2C3D.F0 clkselect_wb_inst/RingOSC_inst/SLICE_661
ROUTE 1 0.631 R2C3D.F0 to R2C3C.D0 clkselect_wb_inst/RingOSC_inst/RingOSCb[2]
CTOF_DEL --- 0.774 R2C3C.D0 to R2C3C.F0 clkselect_wb_inst/RingOSC_inst/SLICE_662
ROUTE 1 0.830 R2C3C.F0 to R2C3C.C1 clkselect_wb_inst/RingOSC_inst/RingOSCb[3]
CTOF_DEL --- 0.774 R2C3C.C1 to R2C3C.F1 clkselect_wb_inst/RingOSC_inst/SLICE_662
ROUTE 1 1.304 R2C3C.F1 to R2C3B.B0 clkselect_wb_inst/RingOSC_inst/RingOSCb[4]
CTOF_DEL --- 0.774 R2C3B.B0 to R2C3B.F0 clkselect_wb_inst/RingOSC_inst/SLICE_663
ROUTE 2 0.871 R2C3B.F0 to R2C3B.C1 clkselect_wb_inst/RingOSC_inst/RingOSCb[5]
CTOF_DEL --- 0.774 R2C3B.C1 to R2C3B.F1 clkselect_wb_inst/RingOSC_inst/SLICE_663
ROUTE 20 7.008 R2C3B.F1 to R3C3C.CLK clkselect_wb_inst/RingOSCraw_c
--------
67.062 (33.9% logic, 66.1% route), 12 logic levels.
Destination Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_479:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.440 OSC.OSC to R8C2A.CLK clkselect_wb_inst/oscclk
--------
7.440 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 415.071ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q clkselect_wb_inst/oscclkclean_inst/CalbrateRingOSC (from clkselect_wb_inst/RingOSCraw_c +)
Destination: FF Data in clkselect_wb_inst/oscclkclean_inst/IntOSCcnt[2] (to clkselect_wb_inst/oscclk +)
Delay: 5.718ns (27.5% logic, 72.5% route), 2 logic levels.
Constraint Details:
5.718ns physical path delay clkselect_wb_inst/oscclkclean_inst/SLICE_470 to clkselect_wb_inst/oscclkclean_inst/SLICE_480 meets
480.769ns delay constraint less
59.622ns skew and
0.358ns DIN_SET requirement (totaling 420.789ns) by 415.071ns
Physical Path Details:
Data path clkselect_wb_inst/oscclkclean_inst/SLICE_470 to clkselect_wb_inst/oscclkclean_inst/SLICE_480:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.801 R3C3C.CLK to R3C3C.Q0 clkselect_wb_inst/oscclkclean_inst/SLICE_470 (from clkselect_wb_inst/RingOSCraw_c)
ROUTE 21 4.143 R3C3C.Q0 to R8C2C.C0 clkselect_wb_inst/CalbrateRingOSC
CTOF_DEL --- 0.774 R8C2C.C0 to R8C2C.F0 clkselect_wb_inst/oscclkclean_inst/SLICE_480
ROUTE 1 0.000 R8C2C.F0 to R8C2C.DI0 clkselect_wb_inst/oscclkclean_inst/N_342_i_i (to clkselect_wb_inst/oscclk)
--------
5.718 (27.5% logic, 72.5% route), 2 logic levels.
Clock Skew Details:
Source Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_470:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.440 OSC.OSC to R3C2D.CLK clkselect_wb_inst/oscclk
REG_DEL --- 0.801 R3C2D.CLK to R3C2D.Q0 clkselect_wb_inst/SLICE_144
ROUTE 2 5.056 R3C2D.Q0 to R4C21D.B1 clkselect_wb_inst/clk_switch_inst1/transfer2
CTOF_DEL --- 0.774 R4C21D.B1 to R4C21D.F1 SLICE_527
ROUTE 289 5.766 R4C21D.F1 to R8C5B.CLK clk
REG_DEL --- 0.801 R8C5B.CLK to R8C5B.Q0 SLICE_340
ROUTE 1 4.265 R8C5B.Q0 to R7C10A.B1 TimeOutStandby
CTOF_DEL --- 0.774 R7C10A.B1 to R7C10A.F1 SLICE_506
ROUTE 1 1.771 R7C10A.F1 to R7C12C.CLK ToggleUSERSTDBY_i
REG_DEL --- 0.801 R7C12C.CLK to R7C12C.Q0 SLICE_417
ROUTE 18 4.788 R7C12C.Q0 to *NTR.USERSTDBY USERSTDBY
STDBY_DEL --- 14.150 *NTR.USERSTDBY to PCNTR.STDBY PowerCntr_inst/PCNTR_Inst0
ROUTE 15 3.757 PCNTR.STDBY to R2C3D.A1 STDBY
CTOF_DEL --- 0.774 R2C3D.A1 to R2C3D.F1 clkselect_wb_inst/RingOSC_inst/SLICE_661
ROUTE 1 0.830 R2C3D.F1 to R2C3D.C0 clkselect_wb_inst/RingOSC_inst/RingOSCb[1]
CTOF_DEL --- 0.774 R2C3D.C0 to R2C3D.F0 clkselect_wb_inst/RingOSC_inst/SLICE_661
ROUTE 1 0.631 R2C3D.F0 to R2C3C.D0 clkselect_wb_inst/RingOSC_inst/RingOSCb[2]
CTOF_DEL --- 0.774 R2C3C.D0 to R2C3C.F0 clkselect_wb_inst/RingOSC_inst/SLICE_662
ROUTE 1 0.830 R2C3C.F0 to R2C3C.C1 clkselect_wb_inst/RingOSC_inst/RingOSCb[3]
CTOF_DEL --- 0.774 R2C3C.C1 to R2C3C.F1 clkselect_wb_inst/RingOSC_inst/SLICE_662
ROUTE 1 1.304 R2C3C.F1 to R2C3B.B0 clkselect_wb_inst/RingOSC_inst/RingOSCb[4]
CTOF_DEL --- 0.774 R2C3B.B0 to R2C3B.F0 clkselect_wb_inst/RingOSC_inst/SLICE_663
ROUTE 2 0.871 R2C3B.F0 to R2C3B.C1 clkselect_wb_inst/RingOSC_inst/RingOSCb[5]
CTOF_DEL --- 0.774 R2C3B.C1 to R2C3B.F1 clkselect_wb_inst/RingOSC_inst/SLICE_663
ROUTE 20 7.008 R2C3B.F1 to R3C3C.CLK clkselect_wb_inst/RingOSCraw_c
--------
67.062 (33.9% logic, 66.1% route), 12 logic levels.
Destination Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_480:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.440 OSC.OSC to R8C2C.CLK clkselect_wb_inst/oscclk
--------
7.440 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 415.071ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q clkselect_wb_inst/oscclkclean_inst/CalbrateRingOSC (from clkselect_wb_inst/RingOSCraw_c +)
Destination: FF Data in clkselect_wb_inst/oscclkclean_inst/IntOSCcnt[1] (to clkselect_wb_inst/oscclk +)
Delay: 5.718ns (27.5% logic, 72.5% route), 2 logic levels.
Constraint Details:
5.718ns physical path delay clkselect_wb_inst/oscclkclean_inst/SLICE_470 to clkselect_wb_inst/oscclkclean_inst/SLICE_479 meets
480.769ns delay constraint less
59.622ns skew and
0.358ns DIN_SET requirement (totaling 420.789ns) by 415.071ns
Physical Path Details:
Data path clkselect_wb_inst/oscclkclean_inst/SLICE_470 to clkselect_wb_inst/oscclkclean_inst/SLICE_479:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.801 R3C3C.CLK to R3C3C.Q0 clkselect_wb_inst/oscclkclean_inst/SLICE_470 (from clkselect_wb_inst/RingOSCraw_c)
ROUTE 21 4.143 R3C3C.Q0 to R8C2A.C1 clkselect_wb_inst/CalbrateRingOSC
CTOF_DEL --- 0.774 R8C2A.C1 to R8C2A.F1 clkselect_wb_inst/oscclkclean_inst/SLICE_479
ROUTE 1 0.000 R8C2A.F1 to R8C2A.DI1 clkselect_wb_inst/oscclkclean_inst/N_398_i_i (to clkselect_wb_inst/oscclk)
--------
5.718 (27.5% logic, 72.5% route), 2 logic levels.
Clock Skew Details:
Source Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_470:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.440 OSC.OSC to R3C2D.CLK clkselect_wb_inst/oscclk
REG_DEL --- 0.801 R3C2D.CLK to R3C2D.Q0 clkselect_wb_inst/SLICE_144
ROUTE 2 5.056 R3C2D.Q0 to R4C21D.B1 clkselect_wb_inst/clk_switch_inst1/transfer2
CTOF_DEL --- 0.774 R4C21D.B1 to R4C21D.F1 SLICE_527
ROUTE 289 5.766 R4C21D.F1 to R8C5B.CLK clk
REG_DEL --- 0.801 R8C5B.CLK to R8C5B.Q0 SLICE_340
ROUTE 1 4.265 R8C5B.Q0 to R7C10A.B1 TimeOutStandby
CTOF_DEL --- 0.774 R7C10A.B1 to R7C10A.F1 SLICE_506
ROUTE 1 1.771 R7C10A.F1 to R7C12C.CLK ToggleUSERSTDBY_i
REG_DEL --- 0.801 R7C12C.CLK to R7C12C.Q0 SLICE_417
ROUTE 18 4.788 R7C12C.Q0 to *NTR.USERSTDBY USERSTDBY
STDBY_DEL --- 14.150 *NTR.USERSTDBY to PCNTR.STDBY PowerCntr_inst/PCNTR_Inst0
ROUTE 15 3.757 PCNTR.STDBY to R2C3D.A1 STDBY
CTOF_DEL --- 0.774 R2C3D.A1 to R2C3D.F1 clkselect_wb_inst/RingOSC_inst/SLICE_661
ROUTE 1 0.830 R2C3D.F1 to R2C3D.C0 clkselect_wb_inst/RingOSC_inst/RingOSCb[1]
CTOF_DEL --- 0.774 R2C3D.C0 to R2C3D.F0 clkselect_wb_inst/RingOSC_inst/SLICE_661
ROUTE 1 0.631 R2C3D.F0 to R2C3C.D0 clkselect_wb_inst/RingOSC_inst/RingOSCb[2]
CTOF_DEL --- 0.774 R2C3C.D0 to R2C3C.F0 clkselect_wb_inst/RingOSC_inst/SLICE_662
ROUTE 1 0.830 R2C3C.F0 to R2C3C.C1 clkselect_wb_inst/RingOSC_inst/RingOSCb[3]
CTOF_DEL --- 0.774 R2C3C.C1 to R2C3C.F1 clkselect_wb_inst/RingOSC_inst/SLICE_662
ROUTE 1 1.304 R2C3C.F1 to R2C3B.B0 clkselect_wb_inst/RingOSC_inst/RingOSCb[4]
CTOF_DEL --- 0.774 R2C3B.B0 to R2C3B.F0 clkselect_wb_inst/RingOSC_inst/SLICE_663
ROUTE 2 0.871 R2C3B.F0 to R2C3B.C1 clkselect_wb_inst/RingOSC_inst/RingOSCb[5]
CTOF_DEL --- 0.774 R2C3B.C1 to R2C3B.F1 clkselect_wb_inst/RingOSC_inst/SLICE_663
ROUTE 20 7.008 R2C3B.F1 to R3C3C.CLK clkselect_wb_inst/RingOSCraw_c
--------
67.062 (33.9% logic, 66.1% route), 12 logic levels.
Destination Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_479:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.440 OSC.OSC to R8C2A.CLK clkselect_wb_inst/oscclk
--------
7.440 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 415.611ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q clkselect_wb_inst/clk_switch_inst1/transfer1 (from clkselect_wb_inst/RingOSCclk +)
Destination: FF Data in clkselect_wb_inst/clk_switch_inst1/capture2 (to clkselect_wb_inst/oscclk +)
Delay: 1.975ns (40.6% logic, 59.4% route), 1 logic levels.
Constraint Details:
1.975ns physical path delay clkselect_wb_inst/SLICE_145 to clkselect_wb_inst/SLICE_146 meets
480.769ns delay constraint less
62.539ns skew and
0.644ns M_SET requirement (totaling 417.586ns) by 415.611ns
Physical Path Details:
Data path clkselect_wb_inst/SLICE_145 to clkselect_wb_inst/SLICE_146:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.801 R3C2C.CLK to R3C2C.Q0 clkselect_wb_inst/SLICE_145 (from clkselect_wb_inst/RingOSCclk)
ROUTE 2 1.174 R3C2C.Q0 to R3C2B.M0 clkselect_wb_inst/clk_switch_inst1/transfer1 (to clkselect_wb_inst/oscclk)
--------
1.975 (40.6% logic, 59.4% route), 1 logic levels.
Clock Skew Details:
Source Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/SLICE_145:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.440 OSC.OSC to R3C2D.CLK clkselect_wb_inst/oscclk
REG_DEL --- 0.801 R3C2D.CLK to R3C2D.Q0 clkselect_wb_inst/SLICE_144
ROUTE 2 5.056 R3C2D.Q0 to R4C21D.B1 clkselect_wb_inst/clk_switch_inst1/transfer2
CTOF_DEL --- 0.774 R4C21D.B1 to R4C21D.F1 SLICE_527
ROUTE 289 5.766 R4C21D.F1 to R8C5B.CLK clk
REG_DEL --- 0.801 R8C5B.CLK to R8C5B.Q0 SLICE_340
ROUTE 1 4.265 R8C5B.Q0 to R7C10A.B1 TimeOutStandby
CTOF_DEL --- 0.774 R7C10A.B1 to R7C10A.F1 SLICE_506
ROUTE 1 1.771 R7C10A.F1 to R7C12C.CLK ToggleUSERSTDBY_i
REG_DEL --- 0.801 R7C12C.CLK to R7C12C.Q0 SLICE_417
ROUTE 18 4.788 R7C12C.Q0 to *NTR.USERSTDBY USERSTDBY
STDBY_DEL --- 14.150 *NTR.USERSTDBY to PCNTR.STDBY PowerCntr_inst/PCNTR_Inst0
ROUTE 15 3.757 PCNTR.STDBY to R2C3D.A1 STDBY
CTOF_DEL --- 0.774 R2C3D.A1 to R2C3D.F1 clkselect_wb_inst/RingOSC_inst/SLICE_661
ROUTE 1 0.830 R2C3D.F1 to R2C3D.C0 clkselect_wb_inst/RingOSC_inst/RingOSCb[1]
CTOF_DEL --- 0.774 R2C3D.C0 to R2C3D.F0 clkselect_wb_inst/RingOSC_inst/SLICE_661
ROUTE 1 0.631 R2C3D.F0 to R2C3C.D0 clkselect_wb_inst/RingOSC_inst/RingOSCb[2]
CTOF_DEL --- 0.774 R2C3C.D0 to R2C3C.F0 clkselect_wb_inst/RingOSC_inst/SLICE_662
ROUTE 1 0.830 R2C3C.F0 to R2C3C.C1 clkselect_wb_inst/RingOSC_inst/RingOSCb[3]
CTOF_DEL --- 0.774 R2C3C.C1 to R2C3C.F1 clkselect_wb_inst/RingOSC_inst/SLICE_662
ROUTE 1 1.304 R2C3C.F1 to R2C3B.B0 clkselect_wb_inst/RingOSC_inst/RingOSCb[4]
CTOF_DEL --- 0.774 R2C3B.B0 to R2C3B.F0 clkselect_wb_inst/RingOSC_inst/SLICE_663
ROUTE 2 0.871 R2C3B.F0 to R2C3B.C1 clkselect_wb_inst/RingOSC_inst/RingOSCb[5]
CTOF_DEL --- 0.774 R2C3B.C1 to R2C3B.F1 clkselect_wb_inst/RingOSC_inst/SLICE_663
ROUTE 20 7.008 R2C3B.F1 to R3C3D.CLK clkselect_wb_inst/RingOSCraw_c
REG_DEL --- 0.801 R3C3D.CLK to R3C3D.Q0 clkselect_wb_inst/oscclkclean_inst/SLICE_473
ROUTE 4 2.116 R3C3D.Q0 to R3C2C.CLK clkselect_wb_inst/RingOSCclk
--------
69.979 (33.6% logic, 66.4% route), 13 logic levels.
Destination Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/SLICE_146:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.440 OSC.OSC to R3C2B.CLK clkselect_wb_inst/oscclk
--------
7.440 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 418.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q clkselect_wb_inst/oscclkclean_inst/CalbrateRingOSC (from clkselect_wb_inst/RingOSCraw_c +)
Destination: FF Data in clkselect_wb_inst/oscclkclean_inst/RingOSCcntstop (to clkselect_wb_inst/oscclk +)
Delay: 2.376ns (33.7% logic, 66.3% route), 1 logic levels.
Constraint Details:
2.376ns physical path delay clkselect_wb_inst/oscclkclean_inst/SLICE_470 to clkselect_wb_inst/oscclkclean_inst/SLICE_143 meets
480.769ns delay constraint less
59.622ns skew and
0.467ns CE_SET requirement (totaling 420.680ns) by 418.304ns
Physical Path Details:
Data path clkselect_wb_inst/oscclkclean_inst/SLICE_470 to clkselect_wb_inst/oscclkclean_inst/SLICE_143:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.801 R3C3C.CLK to R3C3C.Q0 clkselect_wb_inst/oscclkclean_inst/SLICE_470 (from clkselect_wb_inst/RingOSCraw_c)
ROUTE 21 1.575 R3C3C.Q0 to R3C3A.CE clkselect_wb_inst/CalbrateRingOSC (to clkselect_wb_inst/oscclk)
--------
2.376 (33.7% logic, 66.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_470:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.440 OSC.OSC to R3C2D.CLK clkselect_wb_inst/oscclk
REG_DEL --- 0.801 R3C2D.CLK to R3C2D.Q0 clkselect_wb_inst/SLICE_144
ROUTE 2 5.056 R3C2D.Q0 to R4C21D.B1 clkselect_wb_inst/clk_switch_inst1/transfer2
CTOF_DEL --- 0.774 R4C21D.B1 to R4C21D.F1 SLICE_527
ROUTE 289 5.766 R4C21D.F1 to R8C5B.CLK clk
REG_DEL --- 0.801 R8C5B.CLK to R8C5B.Q0 SLICE_340
ROUTE 1 4.265 R8C5B.Q0 to R7C10A.B1 TimeOutStandby
CTOF_DEL --- 0.774 R7C10A.B1 to R7C10A.F1 SLICE_506
ROUTE 1 1.771 R7C10A.F1 to R7C12C.CLK ToggleUSERSTDBY_i
REG_DEL --- 0.801 R7C12C.CLK to R7C12C.Q0 SLICE_417
ROUTE 18 4.788 R7C12C.Q0 to *NTR.USERSTDBY USERSTDBY
STDBY_DEL --- 14.150 *NTR.USERSTDBY to PCNTR.STDBY PowerCntr_inst/PCNTR_Inst0
ROUTE 15 3.757 PCNTR.STDBY to R2C3D.A1 STDBY
CTOF_DEL --- 0.774 R2C3D.A1 to R2C3D.F1 clkselect_wb_inst/RingOSC_inst/SLICE_661
ROUTE 1 0.830 R2C3D.F1 to R2C3D.C0 clkselect_wb_inst/RingOSC_inst/RingOSCb[1]
CTOF_DEL --- 0.774 R2C3D.C0 to R2C3D.F0 clkselect_wb_inst/RingOSC_inst/SLICE_661
ROUTE 1 0.631 R2C3D.F0 to R2C3C.D0 clkselect_wb_inst/RingOSC_inst/RingOSCb[2]
CTOF_DEL --- 0.774 R2C3C.D0 to R2C3C.F0 clkselect_wb_inst/RingOSC_inst/SLICE_662
ROUTE 1 0.830 R2C3C.F0 to R2C3C.C1 clkselect_wb_inst/RingOSC_inst/RingOSCb[3]
CTOF_DEL --- 0.774 R2C3C.C1 to R2C3C.F1 clkselect_wb_inst/RingOSC_inst/SLICE_662
ROUTE 1 1.304 R2C3C.F1 to R2C3B.B0 clkselect_wb_inst/RingOSC_inst/RingOSCb[4]
CTOF_DEL --- 0.774 R2C3B.B0 to R2C3B.F0 clkselect_wb_inst/RingOSC_inst/SLICE_663
ROUTE 2 0.871 R2C3B.F0 to R2C3B.C1 clkselect_wb_inst/RingOSC_inst/RingOSCb[5]
CTOF_DEL --- 0.774 R2C3B.C1 to R2C3B.F1 clkselect_wb_inst/RingOSC_inst/SLICE_663
ROUTE 20 7.008 R2C3B.F1 to R3C3C.CLK clkselect_wb_inst/RingOSCraw_c
--------
67.062 (33.9% logic, 66.1% route), 12 logic levels.
Destination Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_143:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.440 OSC.OSC to R3C3A.CLK clkselect_wb_inst/oscclk
--------
7.440 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 459.260ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q USBorBatt (from clk +)
Destination: FF Data in clkselect_wb_inst/clk_switch_inst1/transfer2 (to clkselect_wb_inst/oscclk +)
Delay: 8.468ns (18.6% logic, 81.4% route), 2 logic levels.
Constraint Details:
8.468ns physical path delay SLICE_20 to clkselect_wb_inst/SLICE_144 meets
(delay constraint based on source clock period of 500.000ns and destination clock period of 480.769ns)
480.769ns delay constraint less
12.397ns skew and
0.644ns M_SET requirement (totaling 467.728ns) by 459.260ns
Physical Path Details:
Data path SLICE_20 to clkselect_wb_inst/SLICE_144:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.801 R5C18A.CLK to R5C18A.Q0 SLICE_20 (from clk)
ROUTE 10 4.264 R5C18A.Q0 to R2C4C.C0 USBorBatt
CTOF_DEL --- 0.774 R2C4C.C0 to R2C4C.F0 clkselect_wb_inst/SLICE_471
ROUTE 8 2.629 R2C4C.F0 to R3C2D.M0 clkselect_wb_inst/N_881_i (to clkselect_wb_inst/oscclk)
--------
8.468 (18.6% logic, 81.4% route), 2 logic levels.
Clock Skew Details:
Source Clock Path clkselect_wb_inst/OSCH_inst to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.440 OSC.OSC to R3C2D.CLK clkselect_wb_inst/oscclk
REG_DEL --- 0.801 R3C2D.CLK to R3C2D.Q0 clkselect_wb_inst/SLICE_144
ROUTE 2 5.056 R3C2D.Q0 to R4C21D.B1 clkselect_wb_inst/clk_switch_inst1/transfer2
CTOF_DEL --- 0.774 R4C21D.B1 to R4C21D.F1 SLICE_527
ROUTE 289 5.766 R4C21D.F1 to R5C18A.CLK clk
--------
19.837 (7.9% logic, 92.1% route), 2 logic levels.
Destination Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/SLICE_144:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.440 OSC.OSC to R3C2D.CLK clkselect_wb_inst/oscclk
--------
7.440 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 461.482ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q clkselect_wb_inst/SelectClockwb (from clk +)
Destination: FF Data in clkselect_wb_inst/clk_switch_inst1/transfer2 (to clkselect_wb_inst/oscclk +)
Delay: 6.246ns (25.2% logic, 74.8% route), 2 logic levels.
Constraint Details:
6.246ns physical path delay clkselect_wb_inst/SLICE_664 to clkselect_wb_inst/SLICE_144 meets
(delay constraint based on source clock period of 500.000ns and destination clock period of 480.769ns)
480.769ns delay constraint less
12.397ns skew and
0.644ns M_SET requirement (totaling 467.728ns) by 461.482ns
Physical Path Details:
Data path clkselect_wb_inst/SLICE_664 to clkselect_wb_inst/SLICE_144:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.801 R2C7D.CLK to R2C7D.Q0 clkselect_wb_inst/SLICE_664 (from clk)
ROUTE 8 2.042 R2C7D.Q0 to R2C4C.D0 clkselect_wb_inst.SelectClockwb
CTOF_DEL --- 0.774 R2C4C.D0 to R2C4C.F0 clkselect_wb_inst/SLICE_471
ROUTE 8 2.629 R2C4C.F0 to R3C2D.M0 clkselect_wb_inst/N_881_i (to clkselect_wb_inst/oscclk)
--------
6.246 (25.2% logic, 74.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/SLICE_664:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.440 OSC.OSC to R3C2D.CLK clkselect_wb_inst/oscclk
REG_DEL --- 0.801 R3C2D.CLK to R3C2D.Q0 clkselect_wb_inst/SLICE_144
ROUTE 2 5.056 R3C2D.Q0 to R4C21D.B1 clkselect_wb_inst/clk_switch_inst1/transfer2
CTOF_DEL --- 0.774 R4C21D.B1 to R4C21D.F1 SLICE_527
ROUTE 289 5.766 R4C21D.F1 to R2C7D.CLK clk
--------
19.837 (7.9% logic, 92.1% route), 2 logic levels.
Destination Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/SLICE_144:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.440 OSC.OSC to R3C2D.CLK clkselect_wb_inst/oscclk
--------
7.440 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 475.240ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q clkselect_wb_inst/oscclkclean_inst/IntOSCcnt[0] (from clkselect_wb_inst/oscclk +)
Destination: FF Data in clkselect_wb_inst/oscclkclean_inst/RingOSCcnten (to clkselect_wb_inst/oscclk +)
Delay: 5.171ns (45.4% logic, 54.6% route), 3 logic levels.
Constraint Details:
5.171ns physical path delay clkselect_wb_inst/oscclkclean_inst/SLICE_479 to clkselect_wb_inst/oscclkclean_inst/SLICE_481 meets
480.769ns delay constraint less
0.000ns skew and
0.358ns DIN_SET requirement (totaling 480.411ns) by 475.240ns
Physical Path Details:
Data path clkselect_wb_inst/oscclkclean_inst/SLICE_479 to clkselect_wb_inst/oscclkclean_inst/SLICE_481:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.801 R8C2A.CLK to R8C2A.Q0 clkselect_wb_inst/oscclkclean_inst/SLICE_479 (from clkselect_wb_inst/oscclk)
ROUTE 4 1.992 R8C2A.Q0 to R8C2B.A1 clkselect_wb_inst/oscclkclean_inst/IntOSCcnt[0]
CTOF_DEL --- 0.774 R8C2B.A1 to R8C2B.F1 clkselect_wb_inst/oscclkclean_inst/SLICE_481
ROUTE 1 0.830 R8C2B.F1 to R8C2B.C0 clkselect_wb_inst/oscclkclean_inst/RingOSCcnten_0_sqmuxa
CTOF_DEL --- 0.774 R8C2B.C0 to R8C2B.F0 clkselect_wb_inst/oscclkclean_inst/SLICE_481
ROUTE 1 0.000 R8C2B.F0 to R8C2B.DI0 clkselect_wb_inst/oscclkclean_inst/N_4168_0 (to clkselect_wb_inst/oscclk)
--------
5.171 (45.4% logic, 54.6% route), 3 logic levels.
Clock Skew Details:
Source Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_479:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.440 OSC.OSC to R8C2A.CLK clkselect_wb_inst/oscclk
--------
7.440 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_481:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.440 OSC.OSC to R8C2B.CLK clkselect_wb_inst/oscclk
--------
7.440 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 475.279ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q clkselect_wb_inst/oscclkclean_inst/IntOSCcnt[2] (from clkselect_wb_inst/oscclk +)
Destination: FF Data in clkselect_wb_inst/oscclkclean_inst/RingOSCcnten (to clkselect_wb_inst/oscclk +)
Delay: 5.132ns (45.8% logic, 54.2% route), 3 logic levels.
Constraint Details:
5.132ns physical path delay clkselect_wb_inst/oscclkclean_inst/SLICE_480 to clkselect_wb_inst/oscclkclean_inst/SLICE_481 meets
480.769ns delay constraint less
0.000ns skew and
0.358ns DIN_SET requirement (totaling 480.411ns) by 475.279ns
Physical Path Details:
Data path clkselect_wb_inst/oscclkclean_inst/SLICE_480 to clkselect_wb_inst/oscclkclean_inst/SLICE_481:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.801 R8C2C.CLK to R8C2C.Q0 clkselect_wb_inst/oscclkclean_inst/SLICE_480 (from clkselect_wb_inst/oscclk)
ROUTE 2 1.953 R8C2C.Q0 to R8C2B.B1 clkselect_wb_inst/oscclkclean_inst/IntOSCcnt[2]
CTOF_DEL --- 0.774 R8C2B.B1 to R8C2B.F1 clkselect_wb_inst/oscclkclean_inst/SLICE_481
ROUTE 1 0.830 R8C2B.F1 to R8C2B.C0 clkselect_wb_inst/oscclkclean_inst/RingOSCcnten_0_sqmuxa
CTOF_DEL --- 0.774 R8C2B.C0 to R8C2B.F0 clkselect_wb_inst/oscclkclean_inst/SLICE_481
ROUTE 1 0.000 R8C2B.F0 to R8C2B.DI0 clkselect_wb_inst/oscclkclean_inst/N_4168_0 (to clkselect_wb_inst/oscclk)
--------
5.132 (45.8% logic, 54.2% route), 3 logic levels.
Clock Skew Details:
Source Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_480:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.440 OSC.OSC to R8C2C.CLK clkselect_wb_inst/oscclk
--------
7.440 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_481:
Name Fanout Delay (ns) Site Resource
ROUTE 7 7.440 OSC.OSC to R8C2B.CLK clkselect_wb_inst/oscclk
--------
7.440 (0.0% logic, 100.0% route), 0 logic levels.
Report: 14.858MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "clk" 2.000000 MHz ; | 2.000 MHz| 16.479 MHz| 2
| | |
FREQUENCY NET | | |
"clkselect_wb_inst/oscclk" 2.080000 MHz | | |
; | 2.080 MHz| 14.858 MHz| 3
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 17 clocks:
Clock Domain: GND Source: SLICE_417.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: clk Source: SLICE_527.F1 Loads: 289
Covered under: FREQUENCY NET "clk" 2.000000 MHz ;
Data transfers from:
Clock Domain: clk_USB_c Source: clk_USB.PAD
Not reported because source and destination domains are unrelated.
Clock Domain: clkselect_wb_inst/RingOSCraw_c Source: clkselect_wb_inst/RingOSC_inst/SLICE_663.F1
Covered under: FREQUENCY NET "clk" 2.000000 MHz ; Transfers: 1
Clock Domain: ToggleUSERSTDBY_i Source: SLICE_506.F1
Covered under: FREQUENCY NET "clk" 2.000000 MHz ; Transfers: 1
Clock Domain: DebounceRingOSCb_c[0] Source: SLICE_687.F0 Loads: 16
No transfer within this clock domain is found
Clock Domain: lcdstate_225 Source: SLICE_686.F1 Loads: 12
No transfer within this clock domain is found
Clock Domain: ButtonPushed Source: PushButton_Debouncer_inst/SLICE_234.Q0 Loads: 3
No transfer within this clock domain is found
Clock Domain: EFB_Inst/i2c1_scli Source: scl.PAD Loads: 1
No transfer within this clock domain is found
Clock Domain: EFB_Inst/spi_clk_i Source: spi_sclk.PAD Loads: 1
No transfer within this clock domain is found
Clock Domain: EFB_Inst/i2c1_sclo Source: EFB_Inst/EFBInst_0.I2C1SCLO Loads: 1
No transfer within this clock domain is found
Clock Domain: EFB_Inst/spi_clk_o Source: EFB_Inst/EFBInst_0.SPISCKO Loads: 1
No transfer within this clock domain is found
Clock Domain: clk_USB_c Source: clk_USB.PAD Loads: 70
No transfer within this clock domain is found
Clock Domain: clkselect_wb_inst/RingOSCclk Source: clkselect_wb_inst/oscclkclean_inst/SLICE_473.Q0 Loads: 4
No transfer within this clock domain is found
Clock Domain: clkselect_wb_inst/oscclk Source: clkselect_wb_inst/OSCH_inst.OSC Loads: 7
Covered under: FREQUENCY NET "clkselect_wb_inst/oscclk" 2.080000 MHz ;
Data transfers from:
Clock Domain: clk Source: SLICE_527.F1
Covered under: FREQUENCY NET "clkselect_wb_inst/oscclk" 2.080000 MHz ; Transfers: 2
Clock Domain: clkselect_wb_inst/RingOSCclk Source: clkselect_wb_inst/oscclkclean_inst/SLICE_473.Q0
Covered under: FREQUENCY NET "clkselect_wb_inst/oscclk" 2.080000 MHz ; Transfers: 1
Clock Domain: clkselect_wb_inst/RingOSCraw_c Source: clkselect_wb_inst/RingOSC_inst/SLICE_663.F1
Covered under: FREQUENCY NET "clkselect_wb_inst/oscclk" 2.080000 MHz ; Transfers: 1
Clock Domain: clkselect_wb_inst/RingOSCraw_c Source: clkselect_wb_inst/RingOSC_inst/SLICE_663.F1 Loads: 20
No transfer within this clock domain is found
Clock Domain: ToggleUSERSTDBY_i Source: SLICE_506.F1 Loads: 1
No transfer within this clock domain is found
Clock Domain: lcdstate[3] Source: SLICE_510.F1 Loads: 12
No transfer within this clock domain is found
Clock Domain: lcdstate[2] Source: SLICE_489.F0 Loads: 4
No transfer within this clock domain is found
Clock Domain: lcdstate_226 Source: SLICE_685.F1 Loads: 12
No transfer within this clock domain is found
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 30244 paths, 2 nets, and 3999 connections (71.9% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond Version 2.0.0.154
Tue Jul 24 16:23:42 2012
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2012 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o Environment_Scanning_impl1.twr Environment_Scanning_impl1.ncd Environment_Scanning_impl1.prf
Design file: environment_scanning_impl1.ncd
Preference file: environment_scanning_impl1.prf
Device,speed: LCMXO2-1200ZE,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "clk" 2.000000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
FREQUENCY NET "clkselect_wb_inst/oscclk" 2.080000 MHz (0 errors) 20 items scored, 0 timing errors detected.
5 potential circuit loops found in timing analysis.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "clk" 2.000000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.374ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q lm8_inst/u1_isp8/u1_isp8_flow_cntl/stack_ptr[2] (from clk +)
Destination: FF Data in lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_0/RAM0 (to clk +)
Delay: 0.703ns (36.6% logic, 63.4% route), 2 logic levels.
Constraint Details:
0.703ns physical path delay lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_130 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_0 meets
0.329ns WAD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.329ns) by 0.374ns
Physical Path Details:
Data path lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_130 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R2C20B.CLK to R2C20B.Q1 lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_130 (from clk)
ROUTE 18 0.446 R2C20B.Q1 to R2C21C.C0 lm8_inst/u1_isp8/u1_isp8_flow_cntl/stack_ptr[2]
ZERO_DEL --- 0.000 R2C21C.C0 to R2C21C.WADO2 lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_0.16
ROUTE 1 0.000 R2C21C.WADO2 to R2C21A.WAD2 lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_0/AD2_INT (to clk)
--------
0.703 (36.6% logic, 63.4% route), 2 logic levels.
Clock Skew Details:
Source Clock Path SLICE_527 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_130:
Name Fanout Delay (ns) Site Resource
ROUTE 289 2.166 R4C21D.F1 to R2C20B.CLK clk
--------
2.166 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_527 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_0:
Name Fanout Delay (ns) Site Resource
ROUTE 289 2.166 R4C21D.F1 to R2C21A.WCK clk
--------
2.166 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.500ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q lm8_inst/u1_isp8/u1_isp8_flow_cntl/stack_ptr[0] (from clk +)
Destination: FF Data in lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_3/RAM0 (to clk +)
FF lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_3/RAM0
Delay: 0.829ns (31.0% logic, 69.0% route), 2 logic levels.
Constraint Details:
0.829ns physical path delay lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_536 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_3 meets
0.329ns WAD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.329ns) by 0.500ns
Physical Path Details:
Data path lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_536 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_3:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R2C20D.CLK to R2C20D.Q0 lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_536 (from clk)
ROUTE 19 0.572 R2C20D.Q0 to R3C20C.A0 lm8_inst/u1_isp8/u1_isp8_flow_cntl/stack_ptr[0]
ZERO_DEL --- 0.000 R3C20C.A0 to R3C20C.WADO0 lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_3.21
ROUTE 2 0.000 R3C20C.WADO0 to R3C20A.WAD0 lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_3/AD0_INT (to clk)
--------
0.829 (31.0% logic, 69.0% route), 2 logic levels.
Clock Skew Details:
Source Clock Path SLICE_527 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_536:
Name Fanout Delay (ns) Site Resource
ROUTE 289 2.166 R4C21D.F1 to R2C20D.CLK clk
--------
2.166 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_527 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_3:
Name Fanout Delay (ns) Site Resource
ROUTE 289 2.166 R4C21D.F1 to R3C20A.WCK clk
--------
2.166 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.500ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q lm8_inst/u1_isp8/u1_isp8_flow_cntl/stack_ptr[0] (from clk +)
Destination: FF Data in lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_3/RAM1 (to clk +)
FF lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_3/RAM1
Delay: 0.829ns (31.0% logic, 69.0% route), 2 logic levels.
Constraint Details:
0.829ns physical path delay lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_536 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_3.22 meets
0.329ns WAD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.329ns) by 0.500ns
Physical Path Details:
Data path lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_536 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_3.22:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R2C20D.CLK to R2C20D.Q0 lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_536 (from clk)
ROUTE 19 0.572 R2C20D.Q0 to R3C20C.A0 lm8_inst/u1_isp8/u1_isp8_flow_cntl/stack_ptr[0]
ZERO_DEL --- 0.000 R3C20C.A0 to R3C20C.WADO0 lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_3.21
ROUTE 2 0.000 R3C20C.WADO0 to R3C20B.WAD0 lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_3/AD0_INT (to clk)
--------
0.829 (31.0% logic, 69.0% route), 2 logic levels.
Clock Skew Details:
Source Clock Path SLICE_527 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_536:
Name Fanout Delay (ns) Site Resource
ROUTE 289 2.166 R4C21D.F1 to R2C20D.CLK clk
--------
2.166 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_527 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_3.22:
Name Fanout Delay (ns) Site Resource
ROUTE 289 2.166 R4C21D.F1 to R3C20B.WCK clk
--------
2.166 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.522ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q lm8_inst/u1_isp8/u1_isp8_flow_cntl/stack_ptr[1] (from clk +)
Destination: FF Data in lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_0/RAM0 (to clk +)
Delay: 0.851ns (30.2% logic, 69.8% route), 2 logic levels.
Constraint Details:
0.851ns physical path delay lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_130 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_0 meets
0.329ns WAD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.329ns) by 0.522ns
Physical Path Details:
Data path lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_130 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R2C20B.CLK to R2C20B.Q0 lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_130 (from clk)
ROUTE 18 0.594 R2C20B.Q0 to R2C21C.B0 lm8_inst/u1_isp8/u1_isp8_flow_cntl/stack_ptr[1]
ZERO_DEL --- 0.000 R2C21C.B0 to R2C21C.WADO1 lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_0.16
ROUTE 1 0.000 R2C21C.WADO1 to R2C21A.WAD1 lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_0/AD1_INT (to clk)
--------
0.851 (30.2% logic, 69.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path SLICE_527 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_130:
Name Fanout Delay (ns) Site Resource
ROUTE 289 2.166 R4C21D.F1 to R2C20B.CLK clk
--------
2.166 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_527 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_0:
Name Fanout Delay (ns) Site Resource
ROUTE 289 2.166 R4C21D.F1 to R2C21A.WCK clk
--------
2.166 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.552ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q lm8_inst/u1_isp8/u1_isp8_flow_cntl/stack_ptr[3] (from clk +)
Destination: FF Data in lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_2/RAM1 (to clk +)
FF lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_2/RAM1
Delay: 0.881ns (29.2% logic, 70.8% route), 2 logic levels.
Constraint Details:
0.881ns physical path delay lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_129 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_2 meets
0.329ns WAD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.329ns) by 0.552ns
Physical Path Details:
Data path lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_129 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_2:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R2C20C.CLK to R2C20C.Q0 lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_129 (from clk)
ROUTE 18 0.624 R2C20C.Q0 to R3C19C.D0 lm8_inst/u1_isp8/u1_isp8_flow_cntl/stack_ptr[3]
ZERO_DEL --- 0.000 R3C19C.D0 to R3C19C.WADO3 lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_2.19
ROUTE 2 0.000 R3C19C.WADO3 to R3C19B.WAD3 lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_2/AD3_INT (to clk)
--------
0.881 (29.2% logic, 70.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path SLICE_527 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_129:
Name Fanout Delay (ns) Site Resource
ROUTE 289 2.166 R4C21D.F1 to R2C20C.CLK clk
--------
2.166 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_527 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_2:
Name Fanout Delay (ns) Site Resource
ROUTE 289 2.166 R4C21D.F1 to R3C19B.WCK clk
--------
2.166 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.552ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q lm8_inst/u1_isp8/u1_isp8_flow_cntl/stack_ptr[3] (from clk +)
Destination: FF Data in lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_2/RAM0 (to clk +)
FF lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_2/RAM0
Delay: 0.881ns (29.2% logic, 70.8% route), 2 logic levels.
Constraint Details:
0.881ns physical path delay lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_129 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_2.20 meets
0.329ns WAD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.329ns) by 0.552ns
Physical Path Details:
Data path lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_129 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_2.20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R2C20C.CLK to R2C20C.Q0 lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_129 (from clk)
ROUTE 18 0.624 R2C20C.Q0 to R3C19C.D0 lm8_inst/u1_isp8/u1_isp8_flow_cntl/stack_ptr[3]
ZERO_DEL --- 0.000 R3C19C.D0 to R3C19C.WADO3 lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_2.19
ROUTE 2 0.000 R3C19C.WADO3 to R3C19A.WAD3 lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_2/AD3_INT (to clk)
--------
0.881 (29.2% logic, 70.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path SLICE_527 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_129:
Name Fanout Delay (ns) Site Resource
ROUTE 289 2.166 R4C21D.F1 to R2C20C.CLK clk
--------
2.166 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_527 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_2.20:
Name Fanout Delay (ns) Site Resource
ROUTE 289 2.166 R4C21D.F1 to R3C19A.WCK clk
--------
2.166 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.624ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q lm8_inst/u1_isp8/u1_isp8_io_cntl/ext_addr[3] (from clk +)
Destination: FF Data in lm8_inst/U2_scratchpad/mem_0_0/RAM1 (to clk +)
FF lm8_inst/U2_scratchpad/mem_0_0/RAM1
Delay: 0.953ns (27.0% logic, 73.0% route), 2 logic levels.
Constraint Details:
0.953ns physical path delay lm8_inst/u1_isp8/u1_isp8_io_cntl/SLICE_442 to lm8_inst/U2_scratchpad/mem_0_0 meets
0.329ns WAD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.329ns) by 0.624ns
Physical Path Details:
Data path lm8_inst/u1_isp8/u1_isp8_io_cntl/SLICE_442 to lm8_inst/U2_scratchpad/mem_0_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R4C12D.CLK to R4C12D.Q1 lm8_inst/u1_isp8/u1_isp8_io_cntl/SLICE_442 (from clk)
ROUTE 25 0.696 R4C12D.Q1 to R4C8C.D0 addr[3]
ZERO_DEL --- 0.000 R4C8C.D0 to R4C8C.WADO3 lm8_inst/U2_scratchpad/mem_0_0.23
ROUTE 2 0.000 R4C8C.WADO3 to R4C8B.WAD3 lm8_inst/U2_scratchpad/mem_0_0/AD3_INT (to clk)
--------
0.953 (27.0% logic, 73.0% route), 2 logic levels.
Clock Skew Details:
Source Clock Path SLICE_527 to lm8_inst/u1_isp8/u1_isp8_io_cntl/SLICE_442:
Name Fanout Delay (ns) Site Resource
ROUTE 289 2.166 R4C21D.F1 to R4C12D.CLK clk
--------
2.166 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_527 to lm8_inst/U2_scratchpad/mem_0_0:
Name Fanout Delay (ns) Site Resource
ROUTE 289 2.166 R4C21D.F1 to R4C8B.WCK clk
--------
2.166 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.624ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q lm8_inst/u1_isp8/u1_isp8_io_cntl/ext_addr[3] (from clk +)
Destination: FF Data in lm8_inst/U2_scratchpad/mem_0_0/RAM0 (to clk +)
FF lm8_inst/U2_scratchpad/mem_0_0/RAM0
Delay: 0.953ns (27.0% logic, 73.0% route), 2 logic levels.
Constraint Details:
0.953ns physical path delay lm8_inst/u1_isp8/u1_isp8_io_cntl/SLICE_442 to lm8_inst/U2_scratchpad/mem_0_0.24 meets
0.329ns WAD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.329ns) by 0.624ns
Physical Path Details:
Data path lm8_inst/u1_isp8/u1_isp8_io_cntl/SLICE_442 to lm8_inst/U2_scratchpad/mem_0_0.24:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R4C12D.CLK to R4C12D.Q1 lm8_inst/u1_isp8/u1_isp8_io_cntl/SLICE_442 (from clk)
ROUTE 25 0.696 R4C12D.Q1 to R4C8C.D0 addr[3]
ZERO_DEL --- 0.000 R4C8C.D0 to R4C8C.WADO3 lm8_inst/U2_scratchpad/mem_0_0.23
ROUTE 2 0.000 R4C8C.WADO3 to R4C8A.WAD3 lm8_inst/U2_scratchpad/mem_0_0/AD3_INT (to clk)
--------
0.953 (27.0% logic, 73.0% route), 2 logic levels.
Clock Skew Details:
Source Clock Path SLICE_527 to lm8_inst/u1_isp8/u1_isp8_io_cntl/SLICE_442:
Name Fanout Delay (ns) Site Resource
ROUTE 289 2.166 R4C21D.F1 to R4C12D.CLK clk
--------
2.166 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_527 to lm8_inst/U2_scratchpad/mem_0_0.24:
Name Fanout Delay (ns) Site Resource
ROUTE 289 2.166 R4C21D.F1 to R4C8A.WCK clk
--------
2.166 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.628ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q lm8_inst/u1_isp8/u1_isp8_flow_cntl/stack_ptr[3] (from clk +)
Destination: FF Data in lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_3/RAM0 (to clk +)
FF lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_3/RAM0
Delay: 0.957ns (26.9% logic, 73.1% route), 2 logic levels.
Constraint Details:
0.957ns physical path delay lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_129 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_3 meets
0.329ns WAD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.329ns) by 0.628ns
Physical Path Details:
Data path lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_129 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_3:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R2C20C.CLK to R2C20C.Q0 lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_129 (from clk)
ROUTE 18 0.700 R2C20C.Q0 to R3C20C.D0 lm8_inst/u1_isp8/u1_isp8_flow_cntl/stack_ptr[3]
ZERO_DEL --- 0.000 R3C20C.D0 to R3C20C.WADO3 lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_3.21
ROUTE 2 0.000 R3C20C.WADO3 to R3C20A.WAD3 lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_3/AD3_INT (to clk)
--------
0.957 (26.9% logic, 73.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path SLICE_527 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_129:
Name Fanout Delay (ns) Site Resource
ROUTE 289 2.166 R4C21D.F1 to R2C20C.CLK clk
--------
2.166 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_527 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_3:
Name Fanout Delay (ns) Site Resource
ROUTE 289 2.166 R4C21D.F1 to R3C20A.WCK clk
--------
2.166 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.628ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q lm8_inst/u1_isp8/u1_isp8_flow_cntl/stack_ptr[3] (from clk +)
Destination: FF Data in lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_0/RAM0 (to clk +)
Delay: 0.957ns (26.9% logic, 73.1% route), 2 logic levels.
Constraint Details:
0.957ns physical path delay lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_129 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_0 meets
0.329ns WAD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.329ns) by 0.628ns
Physical Path Details:
Data path lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_129 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R2C20C.CLK to R2C20C.Q0 lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_129 (from clk)
ROUTE 18 0.700 R2C20C.Q0 to R2C21C.D0 lm8_inst/u1_isp8/u1_isp8_flow_cntl/stack_ptr[3]
ZERO_DEL --- 0.000 R2C21C.D0 to R2C21C.WADO3 lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_0.16
ROUTE 1 0.000 R2C21C.WADO3 to R2C21A.WAD3 lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_0/AD3_INT (to clk)
--------
0.957 (26.9% logic, 73.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path SLICE_527 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/SLICE_129:
Name Fanout Delay (ns) Site Resource
ROUTE 289 2.166 R4C21D.F1 to R2C20C.CLK clk
--------
2.166 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_527 to lm8_inst/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_0:
Name Fanout Delay (ns) Site Resource
ROUTE 289 2.166 R4C21D.F1 to R2C21A.WCK clk
--------
2.166 (0.0% logic, 100.0% route), 0 logic levels.
================================================================================
Preference: FREQUENCY NET "clkselect_wb_inst/oscclk" 2.080000 MHz ;
20 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.788ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q clkselect_wb_inst/clk_switch_inst1/capture2 (from clkselect_wb_inst/oscclk +)
Destination: FF Data in clkselect_wb_inst/clk_switch_inst1/transfer2 (to clkselect_wb_inst/oscclk +)
Delay: 0.690ns (37.2% logic, 62.8% route), 1 logic levels.
Constraint Details:
0.690ns physical path delay clkselect_wb_inst/SLICE_146 to clkselect_wb_inst/SLICE_144 meets
-0.098ns LSR_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.098ns) by 0.788ns
Physical Path Details:
Data path clkselect_wb_inst/SLICE_146 to clkselect_wb_inst/SLICE_144:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R3C2B.CLK to R3C2B.Q0 clkselect_wb_inst/SLICE_146 (from clkselect_wb_inst/oscclk)
ROUTE 1 0.433 R3C2B.Q0 to R3C2D.LSR clkselect_wb_inst/clk_switch_inst1/capture2 (to clkselect_wb_inst/oscclk)
--------
0.690 (37.2% logic, 62.8% route), 1 logic levels.
Clock Skew Details:
Source Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/SLICE_146:
Name Fanout Delay (ns) Site Resource
ROUTE 7 2.866 OSC.OSC to R3C2B.CLK clkselect_wb_inst/oscclk
--------
2.866 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/SLICE_144:
Name Fanout Delay (ns) Site Resource
ROUTE 7 2.866 OSC.OSC to R3C2D.CLK clkselect_wb_inst/oscclk
--------
2.866 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.856ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q clkselect_wb_inst/oscclkclean_inst/RingOSCcnten (from clkselect_wb_inst/oscclk +)
Destination: FF Data in clkselect_wb_inst/oscclkclean_inst/RingOSCcnten (to clkselect_wb_inst/oscclk +)
Delay: 0.824ns (55.3% logic, 44.7% route), 2 logic levels.
Constraint Details:
0.824ns physical path delay clkselect_wb_inst/oscclkclean_inst/SLICE_481 to clkselect_wb_inst/oscclkclean_inst/SLICE_481 meets
-0.032ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.032ns) by 0.856ns
Physical Path Details:
Data path clkselect_wb_inst/oscclkclean_inst/SLICE_481 to clkselect_wb_inst/oscclkclean_inst/SLICE_481:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R8C2B.CLK to R8C2B.Q0 clkselect_wb_inst/oscclkclean_inst/SLICE_481 (from clkselect_wb_inst/oscclk)
ROUTE 3 0.368 R8C2B.Q0 to R8C2B.A0 clkselect_wb_inst/oscclkclean_inst/RingOSCcnten
CTOF_DEL --- 0.199 R8C2B.A0 to R8C2B.F0 clkselect_wb_inst/oscclkclean_inst/SLICE_481
ROUTE 1 0.000 R8C2B.F0 to R8C2B.DI0 clkselect_wb_inst/oscclkclean_inst/N_4168_0 (to clkselect_wb_inst/oscclk)
--------
0.824 (55.3% logic, 44.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_481:
Name Fanout Delay (ns) Site Resource
ROUTE 7 2.866 OSC.OSC to R8C2B.CLK clkselect_wb_inst/oscclk
--------
2.866 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_481:
Name Fanout Delay (ns) Site Resource
ROUTE 7 2.866 OSC.OSC to R8C2B.CLK clkselect_wb_inst/oscclk
--------
2.866 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.856ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q clkselect_wb_inst/oscclkclean_inst/IntOSCcnt[2] (from clkselect_wb_inst/oscclk +)
Destination: FF Data in clkselect_wb_inst/oscclkclean_inst/IntOSCcnt[2] (to clkselect_wb_inst/oscclk +)
Delay: 0.824ns (55.3% logic, 44.7% route), 2 logic levels.
Constraint Details:
0.824ns physical path delay clkselect_wb_inst/oscclkclean_inst/SLICE_480 to clkselect_wb_inst/oscclkclean_inst/SLICE_480 meets
-0.032ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.032ns) by 0.856ns
Physical Path Details:
Data path clkselect_wb_inst/oscclkclean_inst/SLICE_480 to clkselect_wb_inst/oscclkclean_inst/SLICE_480:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R8C2C.CLK to R8C2C.Q0 clkselect_wb_inst/oscclkclean_inst/SLICE_480 (from clkselect_wb_inst/oscclk)
ROUTE 2 0.368 R8C2C.Q0 to R8C2C.A0 clkselect_wb_inst/oscclkclean_inst/IntOSCcnt[2]
CTOF_DEL --- 0.199 R8C2C.A0 to R8C2C.F0 clkselect_wb_inst/oscclkclean_inst/SLICE_480
ROUTE 1 0.000 R8C2C.F0 to R8C2C.DI0 clkselect_wb_inst/oscclkclean_inst/N_342_i_i (to clkselect_wb_inst/oscclk)
--------
0.824 (55.3% logic, 44.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_480:
Name Fanout Delay (ns) Site Resource
ROUTE 7 2.866 OSC.OSC to R8C2C.CLK clkselect_wb_inst/oscclk
--------
2.866 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_480:
Name Fanout Delay (ns) Site Resource
ROUTE 7 2.866 OSC.OSC to R8C2C.CLK clkselect_wb_inst/oscclk
--------
2.866 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.857ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q clkselect_wb_inst/oscclkclean_inst/IntOSCcnt[0] (from clkselect_wb_inst/oscclk +)
Destination: FF Data in clkselect_wb_inst/oscclkclean_inst/IntOSCcnt[0] (to clkselect_wb_inst/oscclk +)
Delay: 0.825ns (55.3% logic, 44.7% route), 2 logic levels.
Constraint Details:
0.825ns physical path delay clkselect_wb_inst/oscclkclean_inst/SLICE_479 to clkselect_wb_inst/oscclkclean_inst/SLICE_479 meets
-0.032ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.032ns) by 0.857ns
Physical Path Details:
Data path clkselect_wb_inst/oscclkclean_inst/SLICE_479 to clkselect_wb_inst/oscclkclean_inst/SLICE_479:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R8C2A.CLK to R8C2A.Q0 clkselect_wb_inst/oscclkclean_inst/SLICE_479 (from clkselect_wb_inst/oscclk)
ROUTE 4 0.369 R8C2A.Q0 to R8C2A.A0 clkselect_wb_inst/oscclkclean_inst/IntOSCcnt[0]
CTOF_DEL --- 0.199 R8C2A.A0 to R8C2A.F0 clkselect_wb_inst/oscclkclean_inst/SLICE_479
ROUTE 1 0.000 R8C2A.F0 to R8C2A.DI0 clkselect_wb_inst/oscclkclean_inst/N_390_i_i (to clkselect_wb_inst/oscclk)
--------
0.825 (55.3% logic, 44.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_479:
Name Fanout Delay (ns) Site Resource
ROUTE 7 2.866 OSC.OSC to R8C2A.CLK clkselect_wb_inst/oscclk
--------
2.866 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_479:
Name Fanout Delay (ns) Site Resource
ROUTE 7 2.866 OSC.OSC to R8C2A.CLK clkselect_wb_inst/oscclk
--------
2.866 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.903ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q clkselect_wb_inst/oscclkclean_inst/IntOSCcnt[1] (from clkselect_wb_inst/oscclk +)
Destination: FF Data in clkselect_wb_inst/oscclkclean_inst/IntOSCcnt[1] (to clkselect_wb_inst/oscclk +)
Delay: 0.871ns (52.4% logic, 47.6% route), 2 logic levels.
Constraint Details:
0.871ns physical path delay clkselect_wb_inst/oscclkclean_inst/SLICE_479 to clkselect_wb_inst/oscclkclean_inst/SLICE_479 meets
-0.032ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.032ns) by 0.903ns
Physical Path Details:
Data path clkselect_wb_inst/oscclkclean_inst/SLICE_479 to clkselect_wb_inst/oscclkclean_inst/SLICE_479:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R8C2A.CLK to R8C2A.Q1 clkselect_wb_inst/oscclkclean_inst/SLICE_479 (from clkselect_wb_inst/oscclk)
ROUTE 3 0.415 R8C2A.Q1 to R8C2A.D1 clkselect_wb_inst/oscclkclean_inst/IntOSCcnt[1]
CTOF_DEL --- 0.199 R8C2A.D1 to R8C2A.F1 clkselect_wb_inst/oscclkclean_inst/SLICE_479
ROUTE 1 0.000 R8C2A.F1 to R8C2A.DI1 clkselect_wb_inst/oscclkclean_inst/N_398_i_i (to clkselect_wb_inst/oscclk)
--------
0.871 (52.4% logic, 47.6% route), 2 logic levels.
Clock Skew Details:
Source Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_479:
Name Fanout Delay (ns) Site Resource
ROUTE 7 2.866 OSC.OSC to R8C2A.CLK clkselect_wb_inst/oscclk
--------
2.866 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_479:
Name Fanout Delay (ns) Site Resource
ROUTE 7 2.866 OSC.OSC to R8C2A.CLK clkselect_wb_inst/oscclk
--------
2.866 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.904ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q clkselect_wb_inst/oscclkclean_inst/IntOSCcnt[0] (from clkselect_wb_inst/oscclk +)
Destination: FF Data in clkselect_wb_inst/oscclkclean_inst/IntOSCcnt[2] (to clkselect_wb_inst/oscclk +)
Delay: 0.872ns (52.3% logic, 47.7% route), 2 logic levels.
Constraint Details:
0.872ns physical path delay clkselect_wb_inst/oscclkclean_inst/SLICE_479 to clkselect_wb_inst/oscclkclean_inst/SLICE_480 meets
-0.032ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.032ns) by 0.904ns
Physical Path Details:
Data path clkselect_wb_inst/oscclkclean_inst/SLICE_479 to clkselect_wb_inst/oscclkclean_inst/SLICE_480:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R8C2A.CLK to R8C2A.Q0 clkselect_wb_inst/oscclkclean_inst/SLICE_479 (from clkselect_wb_inst/oscclk)
ROUTE 4 0.416 R8C2A.Q0 to R8C2C.D0 clkselect_wb_inst/oscclkclean_inst/IntOSCcnt[0]
CTOF_DEL --- 0.199 R8C2C.D0 to R8C2C.F0 clkselect_wb_inst/oscclkclean_inst/SLICE_480
ROUTE 1 0.000 R8C2C.F0 to R8C2C.DI0 clkselect_wb_inst/oscclkclean_inst/N_342_i_i (to clkselect_wb_inst/oscclk)
--------
0.872 (52.3% logic, 47.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_479:
Name Fanout Delay (ns) Site Resource
ROUTE 7 2.866 OSC.OSC to R8C2A.CLK clkselect_wb_inst/oscclk
--------
2.866 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_480:
Name Fanout Delay (ns) Site Resource
ROUTE 7 2.866 OSC.OSC to R8C2C.CLK clkselect_wb_inst/oscclk
--------
2.866 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.050ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q clkselect_wb_inst/oscclkclean_inst/IntOSCcnt[0] (from clkselect_wb_inst/oscclk +)
Destination: FF Data in clkselect_wb_inst/oscclkclean_inst/IntOSCcnt[1] (to clkselect_wb_inst/oscclk +)
Delay: 1.018ns (44.8% logic, 55.2% route), 2 logic levels.
Constraint Details:
1.018ns physical path delay clkselect_wb_inst/oscclkclean_inst/SLICE_479 to clkselect_wb_inst/oscclkclean_inst/SLICE_479 meets
-0.032ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.032ns) by 1.050ns
Physical Path Details:
Data path clkselect_wb_inst/oscclkclean_inst/SLICE_479 to clkselect_wb_inst/oscclkclean_inst/SLICE_479:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R8C2A.CLK to R8C2A.Q0 clkselect_wb_inst/oscclkclean_inst/SLICE_479 (from clkselect_wb_inst/oscclk)
ROUTE 4 0.562 R8C2A.Q0 to R8C2A.A1 clkselect_wb_inst/oscclkclean_inst/IntOSCcnt[0]
CTOF_DEL --- 0.199 R8C2A.A1 to R8C2A.F1 clkselect_wb_inst/oscclkclean_inst/SLICE_479
ROUTE 1 0.000 R8C2A.F1 to R8C2A.DI1 clkselect_wb_inst/oscclkclean_inst/N_398_i_i (to clkselect_wb_inst/oscclk)
--------
1.018 (44.8% logic, 55.2% route), 2 logic levels.
Clock Skew Details:
Source Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_479:
Name Fanout Delay (ns) Site Resource
ROUTE 7 2.866 OSC.OSC to R8C2A.CLK clkselect_wb_inst/oscclk
--------
2.866 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_479:
Name Fanout Delay (ns) Site Resource
ROUTE 7 2.866 OSC.OSC to R8C2A.CLK clkselect_wb_inst/oscclk
--------
2.866 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.079ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q clkselect_wb_inst/oscclkclean_inst/IntOSCcnt[1] (from clkselect_wb_inst/oscclk +)
Destination: FF Data in clkselect_wb_inst/oscclkclean_inst/IntOSCcnt[2] (to clkselect_wb_inst/oscclk +)
Delay: 1.047ns (43.6% logic, 56.4% route), 2 logic levels.
Constraint Details:
1.047ns physical path delay clkselect_wb_inst/oscclkclean_inst/SLICE_479 to clkselect_wb_inst/oscclkclean_inst/SLICE_480 meets
-0.032ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.032ns) by 1.079ns
Physical Path Details:
Data path clkselect_wb_inst/oscclkclean_inst/SLICE_479 to clkselect_wb_inst/oscclkclean_inst/SLICE_480:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R8C2A.CLK to R8C2A.Q1 clkselect_wb_inst/oscclkclean_inst/SLICE_479 (from clkselect_wb_inst/oscclk)
ROUTE 3 0.591 R8C2A.Q1 to R8C2C.B0 clkselect_wb_inst/oscclkclean_inst/IntOSCcnt[1]
CTOF_DEL --- 0.199 R8C2C.B0 to R8C2C.F0 clkselect_wb_inst/oscclkclean_inst/SLICE_480
ROUTE 1 0.000 R8C2C.F0 to R8C2C.DI0 clkselect_wb_inst/oscclkclean_inst/N_342_i_i (to clkselect_wb_inst/oscclk)
--------
1.047 (43.6% logic, 56.4% route), 2 logic levels.
Clock Skew Details:
Source Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_479:
Name Fanout Delay (ns) Site Resource
ROUTE 7 2.866 OSC.OSC to R8C2A.CLK clkselect_wb_inst/oscclk
--------
2.866 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_480:
Name Fanout Delay (ns) Site Resource
ROUTE 7 2.866 OSC.OSC to R8C2C.CLK clkselect_wb_inst/oscclk
--------
2.866 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.257ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q clkselect_wb_inst/oscclkclean_inst/RingOSCcnten (from clkselect_wb_inst/oscclk +)
Destination: FF Data in clkselect_wb_inst/oscclkclean_inst/RingOSCcntstop (to clkselect_wb_inst/oscclk +)
Delay: 1.190ns (21.6% logic, 78.4% route), 1 logic levels.
Constraint Details:
1.190ns physical path delay clkselect_wb_inst/oscclkclean_inst/SLICE_481 to clkselect_wb_inst/oscclkclean_inst/SLICE_143 meets
-0.067ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.067ns) by 1.257ns
Physical Path Details:
Data path clkselect_wb_inst/oscclkclean_inst/SLICE_481 to clkselect_wb_inst/oscclkclean_inst/SLICE_143:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R8C2B.CLK to R8C2B.Q0 clkselect_wb_inst/oscclkclean_inst/SLICE_481 (from clkselect_wb_inst/oscclk)
ROUTE 3 0.933 R8C2B.Q0 to R3C3A.M0 clkselect_wb_inst/oscclkclean_inst/RingOSCcnten (to clkselect_wb_inst/oscclk)
--------
1.190 (21.6% logic, 78.4% route), 1 logic levels.
Clock Skew Details:
Source Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_481:
Name Fanout Delay (ns) Site Resource
ROUTE 7 2.866 OSC.OSC to R8C2B.CLK clkselect_wb_inst/oscclk
--------
2.866 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_143:
Name Fanout Delay (ns) Site Resource
ROUTE 7 2.866 OSC.OSC to R3C3A.CLK clkselect_wb_inst/oscclk
--------
2.866 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.499ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q clkselect_wb_inst/oscclkclean_inst/IntOSCcnt[0] (from clkselect_wb_inst/oscclk +)
Destination: FF Data in clkselect_wb_inst/oscclkclean_inst/RingOSCcnten (to clkselect_wb_inst/oscclk +)
Delay: 1.467ns (44.6% logic, 55.4% route), 3 logic levels.
Constraint Details:
1.467ns physical path delay clkselect_wb_inst/oscclkclean_inst/SLICE_479 to clkselect_wb_inst/oscclkclean_inst/SLICE_481 meets
-0.032ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.032ns) by 1.499ns
Physical Path Details:
Data path clkselect_wb_inst/oscclkclean_inst/SLICE_479 to clkselect_wb_inst/oscclkclean_inst/SLICE_481:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R8C2A.CLK to R8C2A.Q0 clkselect_wb_inst/oscclkclean_inst/SLICE_479 (from clkselect_wb_inst/oscclk)
ROUTE 4 0.567 R8C2A.Q0 to R8C2B.A1 clkselect_wb_inst/oscclkclean_inst/IntOSCcnt[0]
CTOF_DEL --- 0.199 R8C2B.A1 to R8C2B.F1 clkselect_wb_inst/oscclkclean_inst/SLICE_481
ROUTE 1 0.245 R8C2B.F1 to R8C2B.C0 clkselect_wb_inst/oscclkclean_inst/RingOSCcnten_0_sqmuxa
CTOF_DEL --- 0.199 R8C2B.C0 to R8C2B.F0 clkselect_wb_inst/oscclkclean_inst/SLICE_481
ROUTE 1 0.000 R8C2B.F0 to R8C2B.DI0 clkselect_wb_inst/oscclkclean_inst/N_4168_0 (to clkselect_wb_inst/oscclk)
--------
1.467 (44.6% logic, 55.4% route), 3 logic levels.
Clock Skew Details:
Source Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_479:
Name Fanout Delay (ns) Site Resource
ROUTE 7 2.866 OSC.OSC to R8C2A.CLK clkselect_wb_inst/oscclk
--------
2.866 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path clkselect_wb_inst/OSCH_inst to clkselect_wb_inst/oscclkclean_inst/SLICE_481:
Name Fanout Delay (ns) Site Resource
ROUTE 7 2.866 OSC.OSC to R8C2B.CLK clkselect_wb_inst/oscclk
--------
2.866 (0.0% logic, 100.0% route), 0 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "clk" 2.000000 MHz ; | -| -| 2
| | |
FREQUENCY NET | | |
"clkselect_wb_inst/oscclk" 2.080000 MHz | | |
; | -| -| 1
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 17 clocks:
Clock Domain: GND Source: SLICE_417.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: clk Source: SLICE_527.F1 Loads: 289
Covered under: FREQUENCY NET "clk" 2.000000 MHz ;
Data transfers from:
Clock Domain: clk_USB_c Source: clk_USB.PAD
Not reported because source and destination domains are unrelated.
Clock Domain: clkselect_wb_inst/RingOSCraw_c Source: clkselect_wb_inst/RingOSC_inst/SLICE_663.F1
Covered under: FREQUENCY NET "clk" 2.000000 MHz ; Transfers: 1
Clock Domain: ToggleUSERSTDBY_i Source: SLICE_506.F1
Covered under: FREQUENCY NET "clk" 2.000000 MHz ; Transfers: 1
Clock Domain: DebounceRingOSCb_c[0] Source: SLICE_687.F0 Loads: 16
No transfer within this clock domain is found
Clock Domain: lcdstate_225 Source: SLICE_686.F1 Loads: 12
No transfer within this clock domain is found
Clock Domain: ButtonPushed Source: PushButton_Debouncer_inst/SLICE_234.Q0 Loads: 3
No transfer within this clock domain is found
Clock Domain: EFB_Inst/i2c1_scli Source: scl.PAD Loads: 1
No transfer within this clock domain is found
Clock Domain: EFB_Inst/spi_clk_i Source: spi_sclk.PAD Loads: 1
No transfer within this clock domain is found
Clock Domain: EFB_Inst/i2c1_sclo Source: EFB_Inst/EFBInst_0.I2C1SCLO Loads: 1
No transfer within this clock domain is found
Clock Domain: EFB_Inst/spi_clk_o Source: EFB_Inst/EFBInst_0.SPISCKO Loads: 1
No transfer within this clock domain is found
Clock Domain: clk_USB_c Source: clk_USB.PAD Loads: 70
No transfer within this clock domain is found
Clock Domain: clkselect_wb_inst/RingOSCclk Source: clkselect_wb_inst/oscclkclean_inst/SLICE_473.Q0 Loads: 4
No transfer within this clock domain is found
Clock Domain: clkselect_wb_inst/oscclk Source: clkselect_wb_inst/OSCH_inst.OSC Loads: 7
Covered under: FREQUENCY NET "clkselect_wb_inst/oscclk" 2.080000 MHz ;
Data transfers from:
Clock Domain: clk Source: SLICE_527.F1
Covered under: FREQUENCY NET "clkselect_wb_inst/oscclk" 2.080000 MHz ; Transfers: 2
Clock Domain: clkselect_wb_inst/RingOSCclk Source: clkselect_wb_inst/oscclkclean_inst/SLICE_473.Q0
Covered under: FREQUENCY NET "clkselect_wb_inst/oscclk" 2.080000 MHz ; Transfers: 1
Clock Domain: clkselect_wb_inst/RingOSCraw_c Source: clkselect_wb_inst/RingOSC_inst/SLICE_663.F1
Covered under: FREQUENCY NET "clkselect_wb_inst/oscclk" 2.080000 MHz ; Transfers: 1
Clock Domain: clkselect_wb_inst/RingOSCraw_c Source: clkselect_wb_inst/RingOSC_inst/SLICE_663.F1 Loads: 20
No transfer within this clock domain is found
Clock Domain: ToggleUSERSTDBY_i Source: SLICE_506.F1 Loads: 1
No transfer within this clock domain is found
Clock Domain: lcdstate[3] Source: SLICE_510.F1 Loads: 12
No transfer within this clock domain is found
Clock Domain: lcdstate[2] Source: SLICE_489.F0 Loads: 4
No transfer within this clock domain is found
Clock Domain: lcdstate_226 Source: SLICE_685.F1 Loads: 12
No transfer within this clock domain is found
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 30237 paths, 2 nets, and 3998 connections (71.9% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------