PAR: Place And Route Diamond Version 2.0.0.154.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2012 Lattice Semiconductor Corporation, All rights reserved.
Tue Jul 24 16:13:53 2012
C:/Diamond/diamond/2.0/ispfpga\bin\nt\par -f Environment_Scanning_impl1.p2t
Environment_Scanning_impl1_map.ncd Environment_Scanning_impl1.dir
Environment_Scanning_impl1.prf
Preference file: Environment_Scanning_impl1.prf.
Cost Table Summary
Level/ Number Timing Run NCD
Cost [ncd] Unrouted Score Time Status
---------- -------- -------- ----- ------------
5_1 * 0 0 19 Complete
* : Design saved.
par done!
Lattice Place and Route Report for Design "Environment_Scanning_impl1_map.ncd"
Tue Jul 24 16:13:53 2012
Best Par Run
PAR: Place And Route Diamond Version 2.0.0.154.
Command Line: C:/Diamond/diamond/2.0/ispfpga\bin\nt\par -f Environment_Scanning_impl1.p2t
Environment_Scanning_impl1_map.ncd Environment_Scanning_impl1.dir
Environment_Scanning_impl1.prf
Preference file: Environment_Scanning_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 3
Loading design for application par from file Environment_Scanning_impl1_map.ncd.
Design name: Environment_Scanning
NCD version: 3.2
Vendor: LATTICE
Device: LCMXO2-1200ZE
Package: CSBGA132
Performance: 3
Loading device for application par from file 'xo2c1200.nph' in environment: C:/Diamond/diamond/2.0/ispfpga.
Package Status: Final Version 1.33
Performance Hardware Data Status: Final Version 22.4
License checked out.
Ignore Preference Error(s): True
Device utilization summary:
PIO (prelim) 36/108 33% used
36/105 34% bonded
IOLOGIC 6/108 5% used
SLICE 640/640 100% used
GSR 1/1 100% used
OSC 1/1 100% used
EBR 6/7 85% used
PCNTR 1/1 100% used
EFB 1/1 100% used
BCINRD 1/4 25% used
5 potential circuit loops found in timing analysis.
Number of Signals: 2053
Number of Connections: 5560
WARNING - par: The SN pin is not available for use as a general purpose I/O pin when the SLAVE_SPI_PORT attribute is enabled. The SN pin should be tied high with an external pull-up if you are not using the Slave SPI port for configuration.
WARNING - par: The PIO comp "sda" has been assigned to pin "B8/PT12D", which is a dual function sysCONFIG pin. This pin will be used during the configuration of the device based on the selected sysCONFIG setting "I2C_PORT=ENABLE". It can be used for logic after configuration. External logic may be needed to avoid contention on this pin.
WARNING - par: The PIO comp "scl" has been assigned to pin "C8/PT12C", which is a dual function sysCONFIG pin. This pin will be used during the configuration of the device based on the selected sysCONFIG setting "I2C_PORT=ENABLE". It can be used for logic after configuration. External logic may be needed to avoid contention on this pin.
WARNING - par: The PIO comp "spi_csn" has been assigned to pin "P3/PB4C", which is a dual function sysCONFIG pin. This pin will be used during the configuration of the device based on the selected sysCONFIG setting "MASTER_SPI_PORT=EFB_USER". It can be used for logic after configuration. External logic may be needed to avoid contention on this pin.
WARNING - par: The PIO comp "spi_sclk" has been assigned to pin "M4/PB6C", which is a dual function sysCONFIG pin. This pin will be used during the configuration of the device based on the selected sysCONFIG setting "MASTER_SPI_PORT=EFB_USER". It can be used for logic after configuration. External logic may be needed to avoid contention on this pin.
WARNING - par: The PIO comp "spi_miso" has been assigned to pin "N4/PB6D", which is a dual function sysCONFIG pin. This pin will be used during the configuration of the device based on the selected sysCONFIG setting "MASTER_SPI_PORT=EFB_USER". It can be used for logic after configuration. External logic may be needed to avoid contention on this pin.
WARNING - par: The PIO comp "spi_mosi" has been assigned to pin "P13/PB20D", which is a dual function sysCONFIG pin. This pin will be used during the configuration of the device based on the selected sysCONFIG setting "MASTER_SPI_PORT=EFB_USER". It can be used for logic after configuration. External logic may be needed to avoid contention on this pin.
WARNING - par: The PIO comp "spi_sclk" has been assigned to pin "M4/PB6C", which is a dual function sysCONFIG pin. This pin will be used during the configuration of the device based on the selected sysCONFIG setting "SLAVE_SPI_PORT=ENABLE". It can be used for logic after configuration. External logic may be needed to avoid contention on this pin.
WARNING - par: The PIO comp "spi_miso" has been assigned to pin "N4/PB6D", which is a dual function sysCONFIG pin. This pin will be used during the configuration of the device based on the selected sysCONFIG setting "SLAVE_SPI_PORT=ENABLE". It can be used for logic after configuration. External logic may be needed to avoid contention on this pin.
WARNING - par: The PIO comp "spi_mosi" has been assigned to pin "P13/PB20D", which is a dual function sysCONFIG pin. This pin will be used during the configuration of the device based on the selected sysCONFIG setting "SLAVE_SPI_PORT=ENABLE". It can be used for logic after configuration. External logic may be needed to avoid contention on this pin.
Pin Constraint Summary:
33 out of 33 pins locked (100% locked).
The following 3 signals are selected to use the primary clock routing resources:
clk_USB_c (driver: clk_USB, clk load #: 70)
clkselect_wb_inst/RingOSCraw_c (driver: clkselect_wb_inst/RingOSC_inst/SLICE_663, clk load #: 20)
DebounceRingOSCb_c[0] (driver: SLICE_687, clk load #: 16)
The following 8 signals are selected to use the secondary clock routing resources:
clk (driver: SLICE_527, clk load #: 288, sr load #: 1, ce load #: 0)
rst_c (driver: rst, clk load #: 0, sr load #: 105, ce load #: 0)
lm8_inst/u1_isp8/rst_n_reg (driver: SLICE_521, clk load #: 0, sr load #: 43, ce load #: 0)
capsense_inst/Recalibrate (driver: capsense_inst/SLICE_451, clk load #: 0, sr load #: 39, ce load #: 0)
USERSTDBY (driver: SLICE_417, clk load #: 0, sr load #: 16, ce load #: 0)
lcdcounter_RNIA65L[0] (driver: SLICE_671, clk load #: 0, sr load #: 0, ce load #: 12)
lcdcounter_2_cry_11_0_RNI9V2D (driver: SLICE_296, clk load #: 0, sr load #: 0, ce load #: 12)
clkselect_wb_inst/oscclk (driver: clkselect_wb_inst/OSCH_inst, clk load #: 6, sr load #: 0, ce load #: 0)
Signal wb_rst is selected as Global Set/Reset.
Starting Placer Phase 0.
..........
Finished Placer Phase 0. REAL time: 4 secs
Starting Placer Phase 1.
...................
Placer score = 373048.
Finished Placer Phase 1. REAL time: 11 secs
Starting Placer Phase 2.
.
Placer score = 371943
Finished Placer Phase 2. REAL time: 11 secs
Clock Report
Global Clock Resources:
CLK_PIN : 2 out of 8 (25%)
PLL : 0 out of 1 (0%)
DCM : 0 out of 2 (0%)
DCC : 0 out of 8 (0%)
Quadrants All (TL, TR, BL, BR) - Global Clocks:
PRIMARY "clk_USB_c" from comp "clk_USB" on CLK_PIN site "A7 (PT12A)", clk load = 70
PRIMARY "clkselect_wb_inst/RingOSCraw_c" from F1 on comp "clkselect_wb_inst/RingOSC_inst/SLICE_663" on site "R2C3B", clk load = 20
PRIMARY "DebounceRingOSCb_c[0]" from F0 on comp "SLICE_687" on site "R7C2A", clk load = 16
SECONDARY "clk" from F1 on comp "SLICE_527" on site "R4C21D", clk load = 288, ce load = 0, sr load = 1
SECONDARY "USERSTDBY" from Q0 on comp "SLICE_417" on site "R7C12C", clk load = 0, ce load = 0, sr load = 16
SECONDARY "rst_c" from comp "rst" on CLK_PIN site "K1 (PL9A)", clk load = 0, ce load = 0, sr load = 105
SECONDARY "lcdcounter_RNIA65L[0]" from F0 on comp "SLICE_671" on site "R7C12B", clk load = 0, ce load = 12, sr load = 0
SECONDARY "lcdcounter_2_cry_11_0_RNI9V2D" from F1 on comp "SLICE_296" on site "R7C14A", clk load = 0, ce load = 12, sr load = 0
SECONDARY "capsense_inst/Recalibrate" from Q0 on comp "capsense_inst/SLICE_451" on site "R7C14B", clk load = 0, ce load = 0, sr load = 39
SECONDARY "lm8_inst/u1_isp8/rst_n_reg" from Q0 on comp "SLICE_521" on site "R7C12A", clk load = 0, ce load = 0, sr load = 43
SECONDARY "clkselect_wb_inst/oscclk" from OSC on comp "clkselect_wb_inst/OSCH_inst" on site "OSC", clk load = 6, ce load = 0, sr load = 0
PRIMARY : 3 out of 8 (37%)
SECONDARY: 8 out of 8 (100%)
Edge Clocks:
No edge clock selected.
I/O Usage Summary (final):
36 out of 108 (33.3%) PIO sites used.
36 out of 105 (34.3%) bonded PIO sites used.
Number of PIO comps: 34; differential: 2
Number of Vref pins used: 0
I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0 | 4 / 26 ( 15%) | 2.5V | - |
| 1 | 12 / 26 ( 46%) | 2.5V | - |
| 2 | 17 / 28 ( 60%) | 2.5V | - |
| 3 | 3 / 25 ( 12%) | 2.5V | - |
+----------+----------------+------------+-----------+
Total placer CPU time: 10 secs
Dumping design to file Environment_Scanning_impl1.dir/5_1.ncd.
5 potential circuit loops found in timing analysis.
0 connections routed; 5560 unrouted.
Starting router resource preassignment
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
Signal=lcdstate_225 loads=12 clock_loads=4
Signal=ButtonPushed loads=3 clock_loads=2
Signal=clkselect_wb_inst/RingOSCclk loads=4 clock_loads=2
Signal=ToggleUSERSTDBY_i loads=1 clock_loads=1
Signal=lcdstate[3] loads=12 clock_loads=4
Signal=lcdstate[2] loads=4 clock_loads=4
Signal=lcdstate_226 loads=12 clock_loads=4
Completed router resource preassignment. Real time: 13 secs
Start NBR router at 16:14:06 07/24/12
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as shorter as possible. The routing process is said
to be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design. Thanks.
*****************************************************************
Start NBR special constraint process at 16:14:06 07/24/12
5 potential circuit loops found in timing analysis.
Start NBR section for initial routing
Level 4, iteration 1
103(0.12%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack: 413.467ns/0.000ns; real time: 16 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing
Level 4, iteration 1
39(0.05%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack: 413.467ns/0.000ns; real time: 16 secs
Level 4, iteration 2
19(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack: 413.467ns/0.000ns; real time: 17 secs
Level 4, iteration 3
4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack: 413.467ns/0.000ns; real time: 17 secs
Level 4, iteration 4
3(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack: 413.467ns/0.000ns; real time: 17 secs
Level 4, iteration 5
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack: 413.467ns/0.000ns; real time: 17 secs
Level 4, iteration 6
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack: 413.467ns/0.000ns; real time: 17 secs
Start NBR section for post-routing
5 potential circuit loops found in timing analysis.
Dumping design to file Environment_Scanning_impl1.dir/5_1.ncd.
End NBR router with 0 unrouted connection
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%)
Estimated worst slack : 413.467ns
Timing score : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
5 potential circuit loops found in timing analysis.
Total CPU time 16 secs
Total REAL time: 18 secs
Completely routed.
End of route. 5560 routed (100.00%); 0 unrouted.
Checking DRC ...
No errors found.
5 potential circuit loops found in timing analysis.
Timing score: 0
Total REAL time to completion: 19 secs
Dumping design to file Environment_Scanning_impl1.dir/5_1.ncd.
All signals are completely routed.
par done!
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2012 Lattice Semiconductor Corporation, All rights reserved.