2-June-2009

POWR605_BOARD_REV_B_readme.txt
for Lattice Semiconductor Corp.

Contact: Chris Dix
(503) 268-8671
christopher.dix@latticesemi.com


ProcessorPM POWR605 Evaluation Board Fabrication Notes

Top & Bottom layers 1oz copper

Inner layers 1 oz copper

Overall thickness 0.064

Gerber Files (in order from top to bottom)

Top Silk Screen    POWR605_BOARD_REV_B-1.SST
Top Solder Paste   POWR605_BOARD_REV_B-1.SPT
Top Solder Mask    POWR605_BOARD_REV_B-1.SMT
Top copper         POWR605_BOARD_REV_B-1.TOP
Power copper       POWR605_BOARD_REV_B-1.PWR
Inner 1 copper     POWR605_BOARD_REV_B-1.IN1
Inner 2 copper     POWR605_BOARD_REV_B-1.IN2
Ground copper      POWR605_BOARD_REV_B-1.GND
Bottom copper      POWR605_BOARD_REV_B-1.BOT
Bot. solder mask   POWR605_BOARD_REV_B-1.SMB
Bot. solder past   POWR605_BOARD_REV_B-1.SPB
Bot. silk screen   POWR605_BOARD_REV_B-1.SSB


White Silk Screen on top and bottom

minimum layer spacing = 0.010

Ground to Power spacing = 0.028
 
minimum hole size = 0.01"

Minimum trace = 0.007

Minimum space = 0.007

No controlled impedances.