#-- Synplicity, Inc.
#-- Version Synplify for Lattice 9.4L
#-- Project file W:\mcr\projects\2008_04_14_4kze_refdesign_cw\run_options.txt
#-- Written on Thu Jun 05 16:34:28 2008


#add_file options
add_file -verilog "C:/ispLEVER_Classic/ispcpld/../cae_library/synthesis/verilog/mach.v"
add_file -verilog "./reference_design_4kze.h"
add_file -verilog "./power_guard.v"
add_file -verilog "./4kze_osc_pg.v"


#implementation: "2008_04_14_4kze_refdesign_cw"
impl -add 2008_04_14_4kze_refdesign_cw -type fpga

#device options
set_option -technology ispmach4000b
set_option -part LC4064B
set_option -package T44C
set_option -speed_grade -2.5

#compilation/mapping options
set_option -default_enum_encoding sequential
set_option -resource_sharing 1
set_option -top_module "top_level"

#map options
set_option -frequency 200.000
set_option -fanin_limit 20
set_option -max_terms_per_macrocell 16
set_option -domap 0
set_option -area_delay_percent 0
set_option -disable_io_insertion 0


#sequential_optimizations options
set_option -symbolic_fsm_compiler 1

#simulation options
set_option -write_verilog 1
set_option -write_vhdl 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./top_level.edi"

#
#implementation attributes

set_option -vlog_std v2001
set_option -num_critical_paths 3
set_option -num_startend_points 0
set_option -auto_constrain_io true
impl -active "2008_04_14_4kze_refdesign_cw"
