This design is intended for use with the ispMACH 4064ZE Evaluation Board. The project files are for use with the ispLEVER Classic 1.1 design tools. This software is avialable for download from: www.latticesemi.com/classic.

For updates to this file, please check the Lattice web site at: www.latticesemi.com/boards, navigate to CPLD boards, and then the appropriate board. 

A quick summary of the operation of this design is as follows:

Users can toggle the switches SW3 on the board and the relative number will display on the LCD. If the user holds down the button J1, the PG enable will be active and block the switch inputs. The clock source for this design is provided by the internal oscillator.