ispLEVER 1.1.00.35.17.08_Obsolete_Pack Fitter Report File
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Project Name : reference_design_4kze Project Path : W:\mcr\Projects\2008_04_14_4kZE_RefDesign_CW Project Fitted on : Thu Jun 05 16:34:43 2008 Device : M4064_64S Package : 144 GLB Input Mux Size : 12 Available Blocks : 4 Speed : -5.8 Part Number : LC4064ZE-5MN144CES Source Format : Pure_Verilog_HDL Project 'reference_design_4kze' Fit Successfully! Compilation_Times
Prefit Time 0 secs Load Design Time 0.13 secs Partition Time 0.05 secs Place Time 0.00 secs Route Time 0.00 secs Total Fit Time 00:00:01 Design_Summary
Total Input Pins 9 Total Logic Functions 37 Total Output Pins 15 Total Bidir I/O Pins 8 Total Buried Nodes 14 Total Flip-Flops 7 Total D Flip-Flops 7 Total T Flip-Flops 0 Total Latches 0 Total Product Terms 34 Total Reserved Pins 0 Total Locked Pins 32 Total Locked Nodes 1 Total Unique Output Enables 1 Total Unique Clocks 1 Total Unique Clock Enables 0 Total Unique Resets 0 Total Unique Presets 0 Fmax Logic Levels - Device_Resource_Summary
Device Total Used Not Used Utilization ----------------------------------------------------------------------- Dedicated Pins Clock/Input Pins 4 0 4 --> 0 Input-Only Pins 6 1 5 --> 16 I/O / Enable Pins 2 0 2 --> 0 I/O Pins 62 31 31 --> 50 Logic Functions 64 37 27 --> 57 Input Registers 64 0 64 --> 0 GLB Inputs 144 20 124 --> 13 Logical Product Terms 320 29 291 --> 9 Occupied GLBs 4 4 0 --> 100 Macrocells 64 24 40 --> 37 Control Product Terms: GLB Clock/Clock Enables 4 1 3 --> 25 GLB Reset/Presets 4 0 4 --> 0 Macrocell Clocks 64 0 64 --> 0 Macrocell Clock Enables 64 0 64 --> 0 Macrocell Enables 64 0 64 --> 0 Macrocell Resets 64 0 64 --> 0 Macrocell Presets 64 0 64 --> 0 Global Routing Pool 144 10 134 --> 6 GRP from IFB .. 1 .. --> .. (from input signals) .. 1 .. --> .. (from output signals) .. 0 .. --> .. (from bidir signals) .. 0 .. --> .. GRP from MFB .. 9 .. --> .. ---------------------------------------------------------------------- <Note> 1 : The available PT is the product term that has not been used. <Note> 2 : IFB is I/O feedback. <Note> 3 : MFB is macrocell feedback. GLB_Resource_Summary
# of PT --- Fanin --- I/O Input Macrocells Macrocells Logic clusters Unique Shared Total Pins Regs Used Inaccessible available PTs used ------------------------------------------------------------------------------------------- Maximum GLB 36 *(1) 8 -- -- 16 80 16 ------------------------------------------------------------------------------------------- GLB A 1 9 10 10/16 0 8 0 8 19 8 GLB B 1 0 1 5/16 0 0 0 16 1 0 GLB C 5 0 5 5/16 0 5 0 11 5 5 GLB D 4 0 4 11/16 0 11 0 5 4 11 ------------------------------------------------------------------------------------------- TOTALS: 11 9 20 31/64 0 24 0 40 29 24 <Note> 1 : For ispMACH 4000 devices, the number of IOs depends on the GLB. <Note> 2 : Four rightmost columns above reflect last status of the placement process. GLB_Control_Summary
Shared Shared | Mcell Mcell Mcell Mcell Mcell Clk/CE Rst/Pr | Clock CE Enable Reset Preset ------------------------------------------------------------------------------ Maximum GLB 1 1 16 16 16 16 16 ============================================================================== GLB A 1 0 0 0 0 0 0 GLB B 0 0 0 0 0 0 0 GLB C 0 0 0 0 0 0 0 GLB D 0 0 0 0 0 0 0 ------------------------------------------------------------------------------ <Note> 1 : For ispMACH 4000 devices, the number of output enables depends on the GLB. Optimizer_and_Fitter_Options
Pin Assignment : Yes Group Assignment : No Pin Reservation : No @Ignore_Project_Constraints : Pin Assignments : No Keep Block Assignment -- Keep Segment Assignment -- Group Assignments : No Macrocell Assignment : No Keep Block Assignment -- Keep Segment Assignment -- @Backannotate_Project_Constraints Pin Assignments : No Pin And Block Assignments : No Pin, Macrocell and Block : No @Timing_Constraints : No @Global_Project_Optimization : Balanced Partitioning : Yes Spread Placement : Yes Note : Pack Design : Balanced Partitioning = No Spread Placement = No Spread Design : Balanced Partitioning = Yes Spread Placement = Yes @Logic_Synthesis : Logic Reduction : Yes Node Collapsing : FMAX Fmax_Logic_Level : 1 D/T Synthesis : Yes XOR Synthesis : Yes Max. P-Term for Collapsing : 16 Max. P-Term for Splitting : 80 Max Symbols : 24 @Utilization_options Max. % of Macrocells used : 100 @Usercode (HEX) @IO_Types Default = LVCMOS18 (2) @Output_Slew_Rate Default = FAST (2) @Power Default = HIGH (2) @Pull Default = PULLUP_DOWN (2) @Input_Registers Default = None (2) @Register_Powerup Default = None Device Options: <Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not follow the drive level set for the Global Configure Unused I/O Option. <Note> 2 : For user-specified constraints on individual signals, refer to the Output, Bidir and Buried Signal Lists. OSCTIMER_Summary
OSCTIMER: Pin/Node OSCTIMER Instance Name I1 Dynamic Disable Signal gnd_n_n Timer Reset Signal gnd_n_n Oscillator Output Clock mfb D-15 osc_clk Timer Output Clock A0_TIMEROUT Oscillator Output Clock Frequency 5.0000 MHz Timer Output Clock Frequency 39.0625 KHz Timer Divider 128 Pinout_Listing
| Pin | Bank |GLB |Assigned| | Signal| | PG Pin No| Type |Number|Pad |Pin | I/O Type | Type | Signal name| Enable -------------------------------------------------------------------------------------- F6 | GND | - | | | | | | A1 | TDI | - | | | | | | E4 | NC | - | | | | | | B2 | NC | - | | | | | | B1 | NC | - | | | | | | C3 | I_O | 0 | A8 | * |LVCMOS18 | Output|LCD_out_4_| C2 | I_O | 0 | A9 | * |LVCMOS18 | Output|LCD_out_3_| C1 | I_O | 0 | A10| * |LVCMOS18 | Output|LCD_out_2_| D1 | I_O | 0 | A11| * |LVCMOS18 | Output|LCD_out_5_| G5 |GNDIO0 | - | | | | | | D2 | NC | - | | | | | | D3 | NC | - | | | | | | E1 | NC | - | | | | | | E2 | I_O | 0 | A12| | | | | F2 | I_O | 0 | A13| | | | | D4 | I_O | 0 | A14| * |LVCMOS18 | Output|LCD_out_6_| F1 | I_O | 0 | A15| | | | | F3 | IN0 | 0 | | | | | | F4 |VCCIO0 | - | | | | | | G1 | I_O | 0 | B15| | | | | E3 | I_O | 0 | B14| | | | | G2 | I_O | 0 | B13| | | | | G3 | I_O | 0 | B12| | | | | H1 | NC | - | | | | | | H3 | NC | - | | | | | | H2 | NC | - | | | | | | H4 |GNDIO0 | - | | | | | | J1 | I_O | 0 | B11| * |LVCMOS18 | Input |button| J3 | I_O | 0 | B10| | | | | J2 | I_O | 0 | B9 | * |LVCMOS18 | Input |switches_0_|button_node K1 | I_O | 0 | B8 | * |LVCMOS18 | Input |switches_2_|button_node K2 | IN1 | 0 | | * |LVCMOS18 | Input |switches_3_|button_node L1 | NC | - | | | | | | G4 | NC | - | | | | | | L2 | TCK | - | | | | | | H5 | VCC | - | | | | | | G6 | GND | - | | | | | | M1 | NC | - | | | | | | K3 | NC | - | | | | | | M2 | NC | - | | | | | | L3 | IN2 | 0 | | | | | | J4 | I_O | 0 | B7 | | | | | K4 | I_O | 0 | B6 | | | | | M3 | I_O | 0 | B5 | | | | | L4 | I_O | 0 | B4 | | | | | H6 |GNDIO0 | - | | | | | | J5 |VCCIO0 | - | | | | | | M4 | NC | - | | | | | | L5 | NC | - | | | | | | K5 | I_O | 0 | B3 | * |LVCMOS18 | Input |switches_5_|button_node J6 | I_O | 0 | B2 | | | | | M5 | I_O | 0 | B1 | * |LVCMOS18 | Input |switches_6_|button_node K6 | I_O | 0 | B0 | | | | | L6 |INCLK1 | 0 | | | | | | H7 | NC | - | | | | | | M6 |INCLK2 | 1 | | | | | | H8 | VCC | - | | | | | | K7 | I_O | 1 | C0 | | | | | M7 | I_O | 1 | C1 | * |LVCMOS18 | Output|LEDs_0_| L7 | I_O | 1 | C2 | * |LVCMOS18 | Output|LEDs_1_| J7 | I_O | 1 | C3 | | | | | L8 | NC | - | | | | | | M8 | NC | - | | | | | | J8 |VCCIO1 | - | | | | | | J9 |GNDIO1 | - | | | | | | M9 | I_O | 1 | C4 | | | | | L9 | I_O | 1 | C5 | * |LVCMOS18 | Output|LEDs_5_| K8 | I_O | 1 | C6 | * |LVCMOS18 | Output|LEDs_6_| M10 | I_O | 1 | C7 | * |LVCMOS18 | Output|LEDs_7_| L10 | NC | - | | | | | | K9 | NC | - | | | | | | M11 | NC | - | | | | | | G7 | GND | - | | | | | | M12 | TMS | - | | | | | | H9 | NC | - | | | | | | L12 | NC | - | | | | | | L11 | NC | - | | | | | | K10 | I_O | 1 | C8 | | | | | K12 | I_O | 1 | C9 | | | | | J10 | I_O | 1 | C10| | | | | K11 | I_O | 1 | C11| | | | | G8 |GNDIO1 | - | | | | | | J12 | NC | - | | | | | | J11 | NC | - | | | | | | H10 | NC | - | | | | | | H12 | I_O | 1 | C12| | | | | G11 | I_O | 1 | C13| | | | | H11 | I_O | 1 | C14| | | | | G12 | I_O | 1 | C15| | | | | G10 | IN3 | 1 | | | | | | G9 |VCCIO1 | - | | | | | | F12 | I_O | 1 | D15| * |LVCMOS18 | Output|LEDs_2_| F11 | I_O | 1 | D14| * |LVCMOS18 | Output|LEDs_3_| E11 | I_O | 1 | D13| * |LVCMOS18 | Input |switches_7_|pgD_button_node E12 | I_O | 1 | D12| * |LVCMOS18 | Output|LEDs_4_| D10 | NC | - | | | | | | F10 | NC | - | | | | | | D12 | NC | - | | | | | | F8 |GNDIO1 | - | | | | | | E10 | I_O | 1 | D11| | | | | D11 | I_O | 1 | D10| | | | | E9 | I_O | 1 | D9 | | | | | C12 | I_O | 1 | D8 | * |LVCMOS18 |Tri-Out|first_18_5_| C11 | IN4 | 1 | | | | | | B12 | NC | - | | | | | | F9 | NC | - | | | | | | B11 | TDO | - | | | | | | E8 | VCC | - | | | | | | F7 | GND | - | | | | | | A12 | NC | - | | | | | | C10 | NC | - | | | | | | B10 | NC | - | | | | | | A11 | IN5 | 1 | | | | | | D9 | I_O | 1 | D7 | * |LVCMOS18 |Tri-Out|first_18_1_| B9 | I_O | 1 | D6 | * |LVCMOS18 |Tri-Out|first_18_4_| C9 | I_O | 1 | D5 | * |LVCMOS18 |Tri-Out|first_18_2_| A10 | I_O | 1 | D4 | * |LVCMOS18 |Tri-Out|first_18_6_| E7 |GNDIO1 | - | | | | | | D8 |VCCIO1 | - | | | | | | A9 | NC | - | | | | | | B8 | NC | - | | | | | | C8 | I_O | 1 | D3 | * |LVCMOS18 |Tri-Out|first_18_3_| A8 | I_O | 1 | D2 | * |LVCMOS18 |Tri-Out|first_18_7_| D7 | I_O | 1 | D1 | | | | | B7 | I_O/OE| 1 | D0 | | | | | C7 |INCLK3 | 1 | | | | | | E6 | NC | - | | | | | | A7 |INCLK0 | 0 | | | | | | E5 | VCC | - | | | | | | D6 | I_O/OE| 0 | A0 | | | | | B6 | I_O | 0 | A1 | | | | | A6 | I_O | 0 | A2 | * |LVCMOS18 | Output|LCD_out_1_| C6 | I_O | 0 | A3 | | | | | B5 | NC | - | | | | | | A5 | NC | - | | | | | | D5 |VCCIO0 | - | | | | | | F5 |GNDIO0 | - | | | | | | A4 | I_O | 0 | A4 | * |LVCMOS18 | Output|LCD_out_0_| B4 | I_O | 0 | A5 | * |LVCMOS18 | Input |switches_4_|pgA_button_node C5 | I_O | 0 | A6 | * |LVCMOS18 | Input |switches_1_|pgA_button_node A3 | I_O | 0 | A7 | * |LVCMOS18 |Tri-Out|first_18_0_| C4 | NC | - | | | | | | B3 | NC | - | | | | | | A2 | NC | - | | | | | | -------------------------------------------------------------------------------------- <Note> GLB Pad : This notation refers to the GLB I/O pad number in the device. <Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins). <Note> Pin Type : ClkIn : Dedicated input or clock pin CLK : Dedicated clock pin I_O : Input/Output pin INP : Dedicated input pin JTAG : JTAG Control and test pin NC : No connected Input_Signal_List
Input Pin Fanout Pin GLB Type Pullup Signal ------------------------------------------ J1 B I/O 3 AB-D Down button J2 B I/O 2 A-C- Down switches_0_ C5 A I/O 2 A-C- Down switches_1_ K1 B I/O 2 A--D Down switches_2_ K2 -- IN 2 A--D Down switches_3_ B4 A I/O 2 A--D Down switches_4_ K5 B I/O 2 A-C- Down switches_5_ M5 B I/O 2 A-C- Down switches_6_ E11 D I/O 2 A-C- Down switches_7_ ------------------------------------------ Output_Signal_List
I C P R P O Output N L Mc R E U C O F B Fanout Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal ------------------------------------------------------------------------ A4 A 8 - 3 1 DFF R ---- Fast Up LCD_out_0_ A6 A 8 - 2 1 DFF R ---- Fast Up LCD_out_1_ C1 A 7 - 3 1 DFF R ---- Fast Up LCD_out_2_ C2 A 9 - 3 1 DFF R ---- Fast Up LCD_out_3_ C3 A 9 - 2 1 DFF R ---- Fast Up LCD_out_4_ D1 A 9 - 3 1 DFF R ---- Fast Up LCD_out_5_ D4 A 9 - 2 1 DFF R ---- Fast Up LCD_out_6_ M7 C 1 2 1 1 COM ---- Fast Down LEDs_0_ L7 C 1 2 1 1 COM ---- Fast Down LEDs_1_ F12 D 1 2 1 1 COM ---- Fast Down LEDs_2_ F11 D 1 2 1 1 COM ---- Fast Down LEDs_3_ E12 D 1 2 1 1 COM ---- Fast Down LEDs_4_ L9 C 1 2 1 1 COM ---- Fast Down LEDs_5_ K8 C 1 2 1 1 COM ---- Fast Down LEDs_6_ M10 C 1 2 1 1 COM ---- Fast Down LEDs_7_ A3 A 0 - 0 1 COM * ---- Fast Up first_18_0_ D9 D 0 - 0 1 COM * ---- Fast Up first_18_1_ C9 D 0 - 0 1 COM * ---- Fast Up first_18_2_ C8 D 0 - 0 1 COM * ---- Fast Up first_18_3_ B9 D 0 - 0 1 COM * ---- Fast Up first_18_4_ C12 D 0 - 0 1 COM * ---- Fast Up first_18_5_ A10 D 0 - 0 1 COM * ---- Fast Up first_18_6_ A8 D 0 - 0 1 COM * ---- Fast Up first_18_7_ ------------------------------------------------------------------------ <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation FP = Fast path used OBP = ORP bypass used Bidir_Signal_List
I C P R P O Bidir N L Mc R E U C O F B Fanout Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal ------------------------------------------------------------------- ------------------------------------------------------------------- <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation FP = Fast path used OBP = ORP bypass used Buried_Signal_List
I C P R P Node N L Mc R E U C I F Fanout Mc GLB P LL PTs S Type E S P E R P Signal ------------------------------------------------------------ -- B 1 - 1 0 COM ---- button_node 15 D 0 - 0 1 COM ---- gnd_n_n -- -- 0 - 0 0 COM ---- leds_c_0__n -- -- 0 - 0 0 COM ---- leds_c_1__n -- -- 0 - 0 0 COM ---- leds_c_2__n -- -- 0 - 0 0 COM ---- leds_c_3__n -- -- 0 - 0 0 COM ---- leds_c_4__n -- -- 0 - 0 0 COM ---- leds_c_5__n -- -- 0 - 0 0 COM ---- leds_c_6__n -- -- 0 - 0 0 COM ---- leds_c_7__n 15 A 0 - 0 0 COM 1 A--- osc_clk -- A 1 - 1 0 COM ---- pgA_button_node -- D 1 - 1 0 COM ---- pgD_button_node ------------------------------------------------------------ <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation IR = Input register FP = Fast path used OBP = ORP bypass used PostFit_Equations
PG(switches_0_, button_node, leds_c_0__n); PG(switches_1_, pgA_button_node, leds_c_1__n); PG(switches_2_, button_node, leds_c_2__n); PG(switches_3_, button_node, leds_c_3__n); PG(switches_4_, pgA_button_node, leds_c_4__n); PG(switches_5_, button_node, leds_c_5__n); PG(switches_6_, button_node, leds_c_6__n); PG(switches_7_, pgD_button_node, leds_c_7__n); LCD_out_0_.D = !leds_c_2__n & leds_c_3__n & leds_c_4__n & leds_c_5__n & leds_c_7__n # !leds_c_1__n & leds_c_3__n & leds_c_4__n & leds_c_5__n & leds_c_7__n # !leds_c_6__n & leds_c_7__n ; (3 pterms, 7 signals) LCD_out_0_.C = osc_clk ; (1 pterm, 1 signal) LCD_out_1_.D = leds_c_1__n & leds_c_2__n & leds_c_3__n & leds_c_4__n & leds_c_5__n & leds_c_7__n # !leds_c_6__n & leds_c_7__n ; (2 pterms, 7 signals) LCD_out_1_.C = osc_clk ; (1 pterm, 1 signal) LCD_out_2_.D = !( leds_c_2__n & leds_c_3__n & leds_c_4__n & leds_c_6__n # !leds_c_5__n & leds_c_6__n # !leds_c_7__n ) ; (3 pterms, 6 signals) LCD_out_2_.C = osc_clk ; (1 pterm, 1 signal) LCD_out_3_.D = !leds_c_0__n & leds_c_1__n & leds_c_2__n & leds_c_4__n & leds_c_5__n & leds_c_7__n # !leds_c_3__n & leds_c_4__n & leds_c_5__n & leds_c_7__n # !leds_c_6__n & leds_c_7__n ; (3 pterms, 8 signals) LCD_out_3_.C = osc_clk ; (1 pterm, 1 signal) LCD_out_4_.D = !leds_c_1__n & leds_c_2__n & leds_c_3__n & leds_c_4__n & leds_c_5__n & leds_c_6__n & leds_c_7__n # !leds_c_0__n & leds_c_2__n & leds_c_3__n & leds_c_4__n & leds_c_5__n & leds_c_6__n & leds_c_7__n ; (2 pterms, 8 signals) LCD_out_4_.C = osc_clk ; (1 pterm, 1 signal) LCD_out_5_.D = !leds_c_0__n & leds_c_1__n & leds_c_2__n & leds_c_3__n & leds_c_6__n & leds_c_7__n # !leds_c_5__n & leds_c_6__n & leds_c_7__n # !leds_c_4__n & leds_c_6__n & leds_c_7__n ; (3 pterms, 8 signals) LCD_out_5_.C = osc_clk ; (1 pterm, 1 signal) LCD_out_6_.D = !leds_c_0__n & leds_c_1__n & leds_c_2__n & leds_c_4__n & leds_c_5__n & leds_c_6__n & leds_c_7__n # !leds_c_3__n & leds_c_4__n & leds_c_5__n & leds_c_6__n & leds_c_7__n ; (2 pterms, 8 signals) LCD_out_6_.C = osc_clk ; (1 pterm, 1 signal) LEDs_0_ = leds_c_0__n ; (1 pterm, 1 signal) LEDs_1_ = leds_c_1__n ; (1 pterm, 1 signal) LEDs_2_ = leds_c_2__n ; (1 pterm, 1 signal) LEDs_3_ = leds_c_3__n ; (1 pterm, 1 signal) LEDs_4_ = leds_c_4__n ; (1 pterm, 1 signal) LEDs_5_ = leds_c_5__n ; (1 pterm, 1 signal) LEDs_6_ = leds_c_6__n ; (1 pterm, 1 signal) LEDs_7_ = leds_c_7__n ; (1 pterm, 1 signal) button_node = button ; (1 pterm, 1 signal) first_18_0_ = 0 ; (0 pterm, 0 signal) first_18_0_.OE = 0 ; (0 pterm, 0 signal) first_18_1_ = 0 ; (0 pterm, 0 signal) first_18_1_.OE = 0 ; (0 pterm, 0 signal) first_18_2_ = 0 ; (0 pterm, 0 signal) first_18_2_.OE = 0 ; (0 pterm, 0 signal) first_18_3_ = 0 ; (0 pterm, 0 signal) first_18_3_.OE = 0 ; (0 pterm, 0 signal) first_18_4_ = 0 ; (0 pterm, 0 signal) first_18_4_.OE = 0 ; (0 pterm, 0 signal) first_18_5_ = 0 ; (0 pterm, 0 signal) first_18_5_.OE = 0 ; (0 pterm, 0 signal) first_18_6_ = 0 ; (0 pterm, 0 signal) first_18_6_.OE = 0 ; (0 pterm, 0 signal) first_18_7_ = 0 ; (0 pterm, 0 signal) first_18_7_.OE = 0 ; (0 pterm, 0 signal) gnd_n_n = 0 ; (0 pterm, 0 signal) pgA_button_node = button ; (1 pterm, 1 signal) pgD_button_node = button ; (1 pterm, 1 signal)