
# This file is used by the simulation model as well as the ispLEVER bitstream
# generation process to automatically initialize the PCS quad to the mode
# selected in the IPexpress. This file is expected to be modified by the
# end user to adjust the PCS quad to the final design requirements.
# channel_0 is in "SERDES Only(10/20-bit)" mode
# channel_1 is in "SERDES Only(10/20-bit)" mode
# channel_2 is in "SERDES Only(10/20-bit)" mode
# channel_3 is in "SERDES Only(10/20-bit)" mode

ch0 13 03  # Powerup Channel
ch1 13 03  # Powerup Channel
ch2 13 03  # Powerup Channel
ch3 13 03  # Powerup Channel
quad 28 50  # Reference clock multiplier
quad 29 01  # default
# quad 02 00  # ref_pclk source is ch0
quad 19 80  # ENABLE word_align_en port, FPGA bus width is 8-bit/10-bit 
quad 18 10  # Serdes 10-bit (8b10b disabled)
quad 14 00  # Always match all word alignment bits
quad 41 00  # de-assert serdes_rst
# quad 15 03  # +ve K
# quad 16 7C  # -ve K
# quad 17 00
ch0 14 90  # 16% pre-emphasis 
ch0 15 10  # +6dB equalization 
ch0 05 03  # 8b10b disabled
ch1 14 90  # 16% pre-emphasis 
ch1 15 10  # +6dB equalization
ch1 05 03  # 8b10b disabled
ch2 14 90  # 16% pre-emphasis 
ch2 15 10  # +6dB equalization
ch2 05 03  # 8b10b disabled
ch3 14 90  # 16% pre-emphasis 
ch3 15 10  # +6dB equalization 
ch3 05 03  # 8b10b disabled


