Description: From
FPGA-TN-02245-1-1-CertusPro-NX-SerDes-PCS-User-Guide of the
Appendix C. Calculating Parameters for SerDes PLL,
it shows the available data rates with respect to the reference clock.
However in any case that the desired data rate for certain reference clock is not available, the user can use the MPCS IP to verify and compute for it.
The user can also manually compute it using the formula provided from Section 6
PLL Clock Setting.
Solution:
For example, looking for 1.25 Gbps and 4.25 Gbps that can be use for 125MHz reference clock.
In G8b10b mode, the refclk = 125MHz could not generate a data rate of 4.25 Gbps.
As seen from the MPCS IP below, the calculated PMA Clock Frequency (FPMA) does not match with the formula FPMA = refclk x F.
When running simulation, the output clock frequency (i.e. rx_out_clk_o) is 125MHz instead of the calculated 106.25 MHz.
Another example, 2.5 Gbps and 4.0 Gbps data rates to use 100 MHz as reference clock.
Checking the 4.0 Gbps data rate at 100MHz, it shows that it need to achieve 100MHz for the output clock frequency.
Since it is a valid PLL settings, the output clock frequency from the simulation matches with the IP GUI.
