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ID: 6304
Case Type: faq
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Family: CrossLink

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By using the hard D-PHY of Crosslink, why does the FREQUENCY PORT declared in the constraint file changed to FREQUENCY NET in the timing analyzer which then generates a warning message?

For hardened blocks like hardened DPHY, the timing analyzer cannot read the hardened blocks once constraining them. In this connection, place-and-route do not really do anything about it. As a recommendation, the designer should constrain the other clocks that are actually used to clock soft logic, like the byte clocks and lpctrl clocks. In this case, it instead changes from port to net instead.