Article Details

ID: 5464
Case Type: faq
Category: Implementation
Related To: Bitstream/JEDEC Generation
Family: Power Manager II

Search Answer Database

Search Text Image

What tools should I use to design code for the CPLD within the POWR1220AT8, and is there any documentation recommended?

The programming file (.jed) for CPLD within the POWR1220AT8 can only be generated using the PAC-Designer tool.
Here is the direct link: http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/MixedSignalDS/PacDesigner

Inside this tool, designers have two options:
1. Use the easy LogiBuilder interface.
2. Use the ABEL window (see application note AN6052 http://www.latticesemi.com/view_document?document_id=6546).
Like most websites, we use cookies and similar technologies to enhance your user experience. We also allow third parties to place cookies on our website. By continuing to use this website you consent to the use of cookies as described in our Cookie Policy.