Article Details

ID: 5428
Case Type: faq
Category: Lattice IP/Reference Design
Related To: IP/Reference Design Inquiries
Family: CrossLink

Search Answer Database

Search Text Image

Why are there still 10 single-ended RX lines even when I configure it to be 8 RX data pairs?

For the simplicity of design, there are always 10 pins that can be seen on the top-level of RTL. Inside the schematic, the last 2 ports is hanging when using 8 RX data.
As for running Place & Route in Diamond producing single-ended RX inputs instead of the desired differential subLVDS inputs, our diamond tool automatically assigns the differential pair (sublvds, lvds, slvs, etc) as long as we specify that pin as differential (IOBUF PORT "clk_p_i" IO_TYPE=SUBLVDS). We don't explicitly assign the negative pin. The tool automatically locks the negative pair so that it can no longer be used by others. In the functional simulations, we only drive the positive pair because the only visible functionality is the positive pin.

In hardware/board level, we drive both positive and negative ports. The user can leave the ports unconnected, or remove the port declaration in the top wrapper (i.e. instance_name.v). The mismatch between the GUI and the generated wrapper fill is resolved in the IP's next release.
Like most websites, we use cookies and similar technologies to enhance your user experience. We also allow third parties to place cookies on our website. By continuing to use this website you consent to the use of cookies as described in our Cookie Policy.