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ID: 3879
Case Type: faq
Category: Implementation
Related To: Synthesis
Family: All FPGA

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Diamond 3.1: Why does the software shows compile issues when multidimensional arrays are packed?

Solution:
If you use Synplify Pro, check the Verilog standard used by the tool. 
 
To check the Verilog standard: 
1. Open Lattice Diamond project.
2. Go to Strategy->Synplify Pro->Verilog Input. 
 
Verilog 2001 standard does not support multidimensional packed array, but it supports multidimensional unpacked array.