Article Details

ID: 3843
Case Type: faq
Category: Lattice IP/Reference Design
Related To: All
Family: All FPGA

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Are Lattice IP (Intellectual Property) reset signals connected to the GSR (Global Set/Reset) modules by default?

The IP (Intellectual Property) reset signals of the Lattice IP cores are not connected to the GSR components by default.

Hence, the users can connect their end design reset signals to the GSR component.