Article Details

ID: 3313
Case Type: faq
Category: Lattice IP/Reference Design
Related To: SGMII and Gb Ethernet PCS
Family: LatticeECP3

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Does Lattice provide any demo/reference design that illustrates connectivity between LatticeECP3 Physical Coding Sublayer (PCS) and Lattice Serial Gigabit Media Independent Interface (SGMII), and Lattice SGMII to Lattice Tri-speed Media Access Controller?

There is no ready demo/reference design for illustrating the connectivity between LatticeECP3 Physical Coding Sublayer (PCS) and Lattice Serial Gigabit Media Independent Interface (SGMII), and Lattice SGMII to Lattice Tri-speed Media Access Controller.

However, you can generate TSMAC Core with SGMII easy connect option and interface with SGMII PCS/SERDES IP.

Refer to the System Block Diagram for the SGMII Easy Connect Option figure in the Tri-Speed Ethernet MAC IP Core User's Guide

http://www.latticesemi.com/view_document?document_id=19224

This provides information on the FPGA system-level block diagram for MAC core instantiation and its usage when configured to support SGMII easy connect mode of operation.

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