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ID: 2466
Case Type: faq
Category: Implementation
Related To: Schematic
Family: All FPGA

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Can I select the type of HDL files generated, verilog or VHDL, for my schematic project?

To select the HDL file type generated from your Schematic, in the Lattice Diamond Design Environment:



  1. Select the Project name in the File List tab in the left window pane

  2. Right Click on the Project name to open the "Project Properties" dialog box

  3. Select the Project name in the Project Properties dialog and  "Schematic HDL Type" will be displayed under Name

  4. Select the value "<default>", "Verilog", or "VHDL", (the system default is Verilog)

  5. Click OK

Lattice Diamond will generate the selected HDL file type during the Synthesis Design process.