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ID: 2463
Case Type: faq
Category: Implementation
Related To: Schematic
Family: All FPGA

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How can I generate a schematic symbol to represent my HDL module?

In order to create a hierarchical design composed of a top-level schematic and HDL modules at lower level you should create schematic symbols from existing HDL modules that will be placed on the top schematic. To generate a schematic symbol for your HDL module:

  1. In Lattice Diamond window, import the HDL module to your project.

  2. Choose Design > Generate Hierarchy, Lattice Diamond displays a graphical view of the design in the HDL Diagram in right window pane.

  3. In the HDL Diagram view, right-click the module that you want to create a symbol from, and choose Generate Schematic Symbol. The Lattice Diamond software writes a new schematic symbol file (*.sym) into the project directory using the interface ports defined by your HDL module.

  4. Finally, you can add the generated symbols into the top schematic by Edit > Add > Symbol in Schematic Editor.