Article Details

ID: 2083
Case Type: faq
Category: Implementation
Related To: Timing Closure
Family: All FPGA

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How do I check the coverage of my timing constraints?

You can look at the end of timing report (*.twr file)


Timing summary (Setup or Hold):
Timing errors: 0  Score: 0
Cumulative negative slack: 0
Constraints cover 1426538 paths, 208 nets, and 170943 connections (89.4% coverage)


Here, the 89.4% is the percentage of the connections that are covered by timing constraints. The coverage is the indication on the path that is covered by constraints. It also tells you that there are 10.6 % paths are not covered. You may need to go over the unconstrained path at least once, to make sure that you are not missing any important constraints for your design.