Article Details

ID: 2022
Case Type: faq
Category: Architecture
Related To: SERDES/PCS
Family: All FPGA

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Do the Lattice XAUI PCS solutions only allow Ethernet frame sizes between 64 and 1518 bytes as specified in IEEE 802.3ae? 

There is no limitation on the Ethernet frame size as far as the Lattice XAUI PCS cores (LatticeSC flexiPCS Core and XAUI PCS IP Core for LatticeECP2M) are concerned. The XAUI PCS cores will allow transmission and reception of any frame size, including jumbo frames. Monitoring frame size and filtering short and jumbo frames is the function of the MAC layer.

On the other hand, The Lattice XAUI PCS cores perform clock rate compensation based on a reference clock frequency of 312.5 MHz \u00B1 100 ppm. Since clock rate compensation involves the addition or removal of  //R// columns during the IDLE phase between frames, you need to avoid transmitting excessively long jumbo frames beyond 9000 bytes. These frames will cause the clock tolerance compensation (CTC) FIFOs to overrun or underrun due to the lack of IDLE codes during the transmission of the long Ethernet frame. The maximum size of an Ethernet jumbo frame that will cause the CTC FIFO to overrrun depends on the CTC FIFO size of the corresponding Lattice XAUI PCS core.