Vol Max is not a user configurable setting. For any of the LVCMOS pin configurations, under normal operating conditions Vol is specified to be a a maximum of 0.4V regardless of the drive strength that the pin was configured. If the current draw falls below 0.1mA, Vol Max will drop to 0.2V or less. This is true for all of the latest Lattice FPGA devices.
Please refer to section sysI/O Single-Ended DC Electrical Characteristics of the datasheet FPGA-DS-02074.