Article Details

ID: 2003
Case Type: faq
Category: Architecture
Related To: IO
Family: LatticeECP3

Search Answer Database

Search Text Image

We are seeing the primary clock delay to multiple IO Logic elements are the same in the LatticeECP3 device, is this correct?

Yes, the primary clock tree to most of the IOLs in the LatticeECP3 is balanced hence you see the delays are almost the same. The only difference you will see is in primary clock tree delays to SERDES pins or IOL pins at the EBR row ends. The primary clock tree delay to rest of the IOLs are all balanced so will be the same.