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ID: 1981
Case Type: faq
Category: Implementation
Related To: Simulation Files
Family: All FPGA

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Is it possible to generate gate level netlist in Lattice Diamond/ispLEVER for evaluating the IP core?

It is not possible to generate gate level netlist in Lattice Diamond/ispLever for Lattice IP without a valid IP license.


You can run functional simulation for Lattice core by using the obfuscated model generated by IP Express.  Typically, this is the *_beh.v file in the generated core directory.  You can refer to the specific IP core User Guide for further detail. 


When you evaluate the core without a license, you can:



  • Run functional simulation

  • Place and route, and generate a bit stream with a hardware timer for your evaluation design

  • Generate timing report for the design